From: Jiaxing Hu <gahing@gahingwoo.com>
To: royalnet026@gmail.com
Cc: tomeu@tomeuvizoso.net, heiko@sntech.de,
chaoyi.chen@rock-chips.com, alchark@flipper.net,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support
Date: Sun, 16 Aug 2026 16:12:33 +1200 [thread overview]
Message-ID: <20260816041233.3566625-1-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260815130556.68876-1-royalnet026@gmail.com>
Hi Igor,
Thank you for running it, and for the unclamped reference.
Your 1001 does not discriminate between the two forms, which I should have said
when I described them. DIV_ROUND_UP(1001,16) is 63, odd, so the parity form
gives 0x80011011 there and so does oc % 32. They differ only where a count is a
multiple of neither 32 nor 16. On RK3576 the failing one was 56, and 88 or 120
would do as well. So your clean result rules nothing out, and I am not reading
it as support either way.
On my side that register turned out to be the whole of it. A 1x1 layer with 56
output channels had timed out in every round it ever ran, 32 of 56, and with
the parity form it is 56 of 56 every channel correct, with the old form
reproducing the timeout in the same log.
You are right about perch.py and there were three of them rather than one. The
inner maxdiff, the interior statistics and the raw row dump all assume a
surface with an interior, and all three raise on a 1x1x1001 classifier after
the useful lines have printed. Fixed here, and checked on the host at 1x1x1001,
5x5x8 and 56x56x64 before flashing, which is a check I should have been running
all along.
And I will re-score operator 28 against the unclamped output. The max(cpu, zp)
reference does move channels that are not wrong, and reading an empty
convolution off it is the kind of mistake I would rather not make twice.
Jiaxing
next prev parent reply other threads:[~2026-08-16 4:12 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 9:40 [PATCH v7 00/10] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-12 9:40 ` [PATCH v7 01/10] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-12 12:47 ` Igor Paunovic
2026-08-12 9:40 ` [PATCH v7 02/10] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-13 7:04 ` Krzysztof Kozlowski
2026-08-12 9:40 ` [PATCH v7 03/10] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-13 7:06 ` Krzysztof Kozlowski
2026-08-14 8:21 ` Jiaxing Hu
2026-08-12 9:40 ` [PATCH v7 04/10] dt-bindings: iommu: rockchip: allow the RK3576 NPU MMU clock set Jiaxing Hu
2026-08-12 10:45 ` Diederik de Haas
2026-08-13 9:27 ` Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 05/10] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 06/10] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 07/10] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-12 12:48 ` Igor Paunovic
2026-08-13 9:26 ` Jiaxing Hu
2026-08-13 9:56 ` Igor Paunovic
2026-08-14 8:26 ` Jiaxing Hu
2026-08-14 11:08 ` Igor Paunovic
[not found] ` <20260814110841.11238-1-royalnet026@gmail.com>
2026-08-15 3:12 ` Jiaxing Hu
2026-08-15 13:05 ` Igor Paunovic
2026-08-16 4:12 ` Jiaxing Hu [this message]
2026-08-12 9:41 ` [PATCH v7 09/10] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-12 9:41 ` [PATCH v7 10/10] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu
2026-08-12 10:20 ` Chaoyi Chen
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