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([2a0a:ef40:f1b:d401:2e0:4cff:fe68:285]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49996106c6esm100527875e9.5.2026.08.16.12.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Aug 2026 12:42:08 -0700 (PDT) From: Dawid Olesinski To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Diederik de Haas , Eric Biggers , Sebastian Reichel , Philipp Zabel , Conor Dooley , Corentin Labbe , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dawid Olesinski Subject: [PATCH v3 3/4] arm64: dts: rockchip: Add crypto node to rk356x-base Date: Sun, 16 Aug 2026 20:39:46 +0100 Message-ID: <20260816194112.552100-4-dawidro@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260816194112.552100-1-dawidro@gmail.com> References: <20260708175837.1718437-1-dawidro@gmail.com> <20260816194112.552100-1-dawidro@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260816_124210_360945_C0C10C65 X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the device tree node for the V2 cryptographic hardware accelerator on RK356x SoCs (RK3566, RK3568). The IP block sits in the non-secure peripheral domain. Its three clocks (core, aclk, hclk) and reset line are accessible directly through the main non-secure CRU, so no firmware intermediary is required. The node is disabled by default; board files that wish to use hardware crypto offload must enable it. Co-developed-by: Corentin Labbe Signed-off-by: Corentin Labbe Signed-off-by: Dawid Olesinski Tested-by: Diederik de Haas # Quartz64-B, NanoPi R5S, NanoPC-T6 LTS --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b7754b..8b88d6de18c2 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1111,6 +1111,17 @@ sdhci: mmc@fe310000 { status = "disabled"; }; + crypto: crypto@fe380000 { + compatible = "rockchip,rk3568-crypto"; + reg = <0x0 0xfe380000 0x0 0x2000>; + interrupts = ; + clocks = <&cru CLK_CRYPTO_NS_CORE>, <&cru ACLK_CRYPTO_NS>, + <&cru HCLK_CRYPTO_NS>; + clock-names = "core", "aclk", "hclk"; + resets = <&cru SRST_CRYPTO_NS_CORE>; + reset-names = "core"; + }; + /* * Testing showed that the HWRNG found in RK3566 produces unacceptably * low quality of random data, so the HWRNG isn't enabled for all RK356x -- 2.47.3