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From: Jiaxing Hu <gahing@gahingwoo.com>
To: tomeu@tomeuvizoso.net, heiko@sntech.de, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, joro@8bytes.org,
	will@kernel.org, robin.murphy@arm.com, ulfh@kernel.org,
	p.zabel@pengutronix.de, ogabbay@kernel.org,
	zhangqing@rock-chips.com
Cc: royalnet026@gmail.com, chaoyi.chen@rock-chips.com,
	diederik@cknow-tech.com, alchark@flipper.net,
	dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org, iommu@lists.linux.dev,
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Jiaxing Hu <gahing@gahingwoo.com>
Subject: [PATCH v8 05/12] dt-bindings: power: rockchip: allow resets in a power domain node
Date: Mon, 17 Aug 2026 23:35:56 +1200	[thread overview]
Message-ID: <20260817113603.1436067-6-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260817113603.1436067-1-gahing@gahingwoo.com>

Some domains do not come up in a usable state on their own and need
their resets cycled once power is on. The RK3576 NPU domains are one
case: without it the first access after power-on takes an async SError.

Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
---
 .../bindings/power/rockchip,power-controller.yaml         | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
index b41db576f..83741f048 100644
--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -136,6 +136,13 @@ $defs:
           A number of phandles to clocks that need to be enabled
           while power domain switches state.
 
+      resets:
+        maxItems: 1
+        description:
+          A phandle to a reset that needs to be cycled once the power domain has
+          been switched on, for domains whose logic does not come up in a usable
+          state by itself.
+
       domain-supply:
         description: domain regulator supply.
 
@@ -216,6 +223,7 @@ examples:
                     reg = <RK3399_PD_IEP>;
                     clocks = <&cru ACLK_IEP>,
                              <&cru HCLK_IEP>;
+                    resets = <&cru SRST_A_IEP>;
                     pm_qos = <&qos_iep>;
                     #power-domain-cells = <0>;
                 };
-- 
2.43.0



  parent reply	other threads:[~2026-08-17 11:37 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-17 11:35 [PATCH v8 00/12] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 01/12] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 02/12] accel/rocket: wait for a running IRQ handler before resetting a core Jiaxing Hu
2026-08-17 12:56   ` Igor Paunovic
2026-08-17 11:35 ` [PATCH v8 03/12] accel/rocket: factor the completion tail out of the IRQ handler Jiaxing Hu
2026-08-17 12:51   ` Igor Paunovic
2026-08-17 11:35 ` [PATCH v8 04/12] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-17 11:35 ` Jiaxing Hu [this message]
2026-08-17 11:35 ` [PATCH v8 06/12] dt-bindings: iommu: rockchip: describe the RK3576 NPU MMU Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 07/12] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-17 11:35 ` [PATCH v8 08/12] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 09/12] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 10/12] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 11/12] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-17 11:36 ` [PATCH v8 12/12] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu

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