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Tue, 18 Aug 2026 03:31:47 -0700 (PDT) Received: from [127.0.0.2] ([188.111.3.154]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499960988c6sm246025575e9.0.2026.08.18.03.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 03:31:46 -0700 (PDT) From: =?utf-8?q?Gr=C3=A9goire_Layet?= Date: Tue, 18 Aug 2026 10:29:16 +0000 Subject: [PATCH v6 3/6] serial: 8250_aspeed_vuart: add VUART over PCI MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260818-aspeed-driver-v6-v6-3-fd7cc0b338ea@9elements.com> References: <20260818-aspeed-driver-v6-v6-0-fd7cc0b338ea@9elements.com> In-Reply-To: <20260818-aspeed-driver-v6-v6-0-fd7cc0b338ea@9elements.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lubomir Rintel , devicetree@vger.kernel.org, Joel Stanley , Andrew Jeffery , Lee Jones , =?utf-8?q?Gr=C3=A9goire_Layet?= , Tan Siewert Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, mfd@lists.linux.dev, andrew@lunn.ch, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, anirudhsriniv@gmail.com, =?utf-8?q?Gr=C3=A9goire_Layet?= X-Mailer: b4 0.15.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260818_033149_316121_C3A90E62 X-CRM114-Status: GOOD ( 25.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the VUART over PCI for the AST2600. Activate it only if the 'aspeed,vuart-over-pci' property flag is set on an 'ast2600-vuart' compatible node. The AST2600 has 2 VUART that are usable over PCI. These are already defined as the VUART3 and VUART4 in the 'aspeed-g6.dtsi'. Sets the BMC PCI device enable bits, sets the PCI class code to unassgined/device specific, and configures MSI interrupts. There is no disable function. Removing this driver should not disable the BMC PCI device, as other drivers could use it. However, if all the drivers using it are removed, the BMC PCI device will still be activated, which is not ideal. But in reality, this is not a use case for a BMC, the drivers will never be removed. This is useful on PCIe BMC expansion cards that use the AST2600, such as the ASUS Kommando IPMI Expansion Card. Register initialisation taken from ASPEED 6.18 Kernel SDK. Add return code checks to each register write. Simplify the code and add macros. The ASPEED_SCUC24 regmap update is use an undefined reserved register ASPEED_SCUC24_RESERVED_14. I was unable to determine the purpose of this bit. In the AST2600 A3 datasheet it is marked as 'reserved'. It is only used on the other revision. As I only have the AST2600A3, I was unable to try this code path. This BIT14 was set in the ASPEED SDK so I kept it. I can remove it and the untested path if necessary. Signed-off-by: Jacky Chou Signed-off-by: aspeedyh Reviewed-by: Tan Siewert Signed-off-by: Grégoire Layet --- drivers/tty/serial/8250/8250_aspeed_vuart.c | 91 +++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c index 6afa2f4057e1..2360d37139bf 100644 --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c @@ -32,6 +32,28 @@ #define ASPEED_VUART_DEFAULT_SIRQ 4 #define ASPEED_VUART_DEFAULT_SIRQ_POLARITY IRQ_TYPE_LEVEL_LOW +#define ASPEED_SCU_SILICON_REVISION_ID 0x04 +#define AST2600A3_REVISION_ID 0x05030303 + +#define ASPEED_SCU_PCIE_CONF_CTRL 0xC20 +#define SCU_PCIE_CONF_BMC_DEV_EN BIT(8) +#define SCU_PCIE_CONF_BMC_DEV_EN_MMIO BIT(9) +#define SCU_PCIE_CONF_BMC_DEV_EN_MSI BIT(11) +#define SCU_PCIE_CONF_BMC_DEV_EN_IRQ BIT(13) +#define SCU_PCIE_CONF_BMC_DEV_EN_PCIE_BUS_MASTER BIT(14) +#define SCU_PCIE_CONF_BMC_DEV_EN_E2L BIT(15) +#define SCU_PCIE_CONF_BMC_DEV_EN_LPC_DECODE BIT(21) + +#define ASPEED_SCUC24 0xC24 +#define ASPEED_SCUC24_MSI_ROUTING_MASK GENMASK(11, 10) +#define ASPEED_SCUC24_MSI_ROUTING_PCIE2LPC_PCIDEV1 \ + FIELD_PREP(ASPEED_SCUC24_MSI_ROUTING_MASK, 2) +#define ASPEED_SCUC24_RESERVED_14 BIT(14) +#define ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN BIT(17) +#define ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN BIT(18) + +#define ASPEED_SCU_BMC_DEV_CLASS 0xC68 + struct aspeed_vuart { struct device *dev; int line; @@ -412,6 +434,66 @@ static int aspeed_vuart_map_irq_polarity(u32 dt) } } +static int aspeed_ast2600_vuart_over_pci_set_enabled(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + u32 silicon_revision_id; + struct regmap *scu; + int rc; + + u32 pcie_config_ctl = SCU_PCIE_CONF_BMC_DEV_EN_IRQ | + SCU_PCIE_CONF_BMC_DEV_EN_MMIO | + SCU_PCIE_CONF_BMC_DEV_EN_MSI | + SCU_PCIE_CONF_BMC_DEV_EN_PCIE_BUS_MASTER | + SCU_PCIE_CONF_BMC_DEV_EN_E2L | + SCU_PCIE_CONF_BMC_DEV_EN_LPC_DECODE | + SCU_PCIE_CONF_BMC_DEV_EN; + + scu = syscon_regmap_lookup_by_phandle(dev->of_node, "aspeed,scu-syscon"); + if (IS_ERR(scu)) { + dev_err(dev, "failed to find SCU regmap\n"); + return PTR_ERR(scu); + } + + /* update class code to be an Unassigned/device specific class device */ + if (regmap_write(scu, ASPEED_SCU_BMC_DEV_CLASS, 0xff000000)) { + dev_err(dev, "could not set PCIe class code\n"); + return -EIO; + } + + if (regmap_update_bits(scu, ASPEED_SCU_PCIE_CONF_CTRL, + pcie_config_ctl, pcie_config_ctl)) { + dev_err(dev, "could not set PCIe configuration\n"); + return -EIO; + } + + if (regmap_read(scu, ASPEED_SCU_SILICON_REVISION_ID, &silicon_revision_id)) { + dev_err(dev, "could not read silicon revision\n"); + return -EIO; + } + + if (silicon_revision_id == AST2600A3_REVISION_ID) + rc = regmap_update_bits(scu, ASPEED_SCUC24, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN | + ASPEED_SCUC24_MSI_ROUTING_MASK, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN | + ASPEED_SCUC24_MSI_ROUTING_PCIE2LPC_PCIDEV1); + else + rc = regmap_update_bits(scu, ASPEED_SCUC24, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN | + ASPEED_SCUC24_RESERVED_14 | + ASPEED_SCUC24_MSI_ROUTING_MASK, + ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN | + ASPEED_SCUC24_RESERVED_14 | + ASPEED_SCUC24_MSI_ROUTING_PCIE2LPC_PCIDEV1); + if (rc) { + dev_err(dev, "could not set PCI device 1 MSI interrupt routing\n"); + return -EIO; + } + + return 0; +} + static int aspeed_vuart_probe(struct platform_device *pdev) { struct of_phandle_args sirq_polarity_sense_args; @@ -540,6 +622,15 @@ static int aspeed_vuart_probe(struct platform_device *pdev) aspeed_vuart_set_host_tx_discard(vuart, true); platform_set_drvdata(pdev, vuart); + if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-vuart") && + of_property_read_bool(dev->of_node, "aspeed,vuart-over-pci")) { + rc = aspeed_ast2600_vuart_over_pci_set_enabled(pdev); + if (rc < 0) { + dev_err_probe(dev, rc, "could not enable VUART over PCI\n"); + goto err_sysfs_remove; + } + } + return 0; err_sysfs_remove: -- 2.54.0