From: Li Dou <li8d6kernel@163.com>
To: maz@kernel.org
Cc: tglx@kernel.org, radu@rendec.net,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, li8d6kernel@163.com
Subject: [PATCH] irqchip/gic-v3: Remove the ISB between AP0Rn and AP1Rn
Date: Mon, 24 Aug 2026 10:34:03 +0800 [thread overview]
Message-ID: <20260824023403.1312-1-li8d6kernel@163.com> (raw)
ARM GICv3 specification says(in section 4.8.4 "System register access to
the Active Priorities registers"):
an ISB is not required between each write to ICC_AP0R<n>_EL1,
Secure ICC_AP1R<n>_EL1, and Non-secure ICC_AP1R<n>_EL1.
It means we can use one ISB after resetting AP0Rn and AP1Rn for context
synchronization. So just remove the previous one.
Signed-off-by: Li Dou <li8d6kernel@163.com>
---
drivers/irqchip/irq-gic-v3.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 6e1fa5b247fc..3c48f46abb25 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1205,8 +1205,6 @@ static void gic_cpu_sys_reg_init(void)
case 4:
write_gicreg(0, ICC_AP0R0_EL1);
}
-
- isb();
}
switch(pribits) {
--
2.43.0
next reply other threads:[~2026-08-24 2:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-24 2:34 Li Dou [this message]
2026-08-24 16:34 ` [PATCH] irqchip/gic-v3: Remove the ISB between AP0Rn and AP1Rn Marc Zyngier
2026-08-25 3:04 ` Li Dou
2026-08-25 7:25 ` Marc Zyngier
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