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[92.247.61.126]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c24968a336fsm1819330866b.60.2026.08.25.06.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 06:54:38 -0700 (PDT) From: Petko Manolov To: linux-media@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Petko Manolov Subject: [PATCH v1 0/1] ARM: dts: draeger: Add devicetrees for Draeger's M48 board. Date: Tue, 25 Aug 2026 16:54:24 +0300 Message-ID: <20260825135426.3967333-1-petko.manolov@konsulko.com> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260825_065442_133244_6A328A6C X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera SoCFPGA Cyclone V” board variant. It has both (the SoC and FPGA) on the same carrier and they are cross-monitoring each other. Petko Manolov (1): ARM: dts: draeger: Add devicetree files for M48 Intel/Altera SoCFPGA Cyclone arch/arm/boot/dts/intel/socfpga/Makefile | 1 + .../socfpga/socfpga_cyclone5_draeger_m48.dts | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts -- 2.47.3