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[82.127.110.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499dc977692sm26009465e9.6.2026.08.26.05.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Aug 2026 05:36:39 -0700 (PDT) From: Amin Gattout Date: Wed, 26 Aug 2026 14:33:50 +0200 Subject: [PATCH 2/2] arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3576 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260826-csi-2-rcv-dts-v1-2-bcd8d459684d@gmail.com> References: <20260826-csi-2-rcv-dts-v1-0-bcd8d459684d@gmail.com> In-Reply-To: <20260826-csi-2-rcv-dts-v1-0-bcd8d459684d@gmail.com> To: Michael Riesch , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Amin Gattout X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1787747795; l=2631; i=amin.gattout@gmail.com; s=20260818; h=from:subject:message-id; bh=qeGW5LpBgkLTF3oueK+lUIcMOPfyOq3EXFr+2a4jTmM=; b=Uj2PG2rjARWU4fhCPtVG8vSsygORspaiXfNPYB4WCs73KwD+d8M6ssdACXnNi68ENOup3DFjM s1X70tpbA9eBuRdXV9fkuL8Bndo7i8tqM7BzdY2UY2JbtcZPkynJ0IS X-Developer-Key: i=amin.gattout@gmail.com; a=ed25519; pk=MSIqDPkCOkwtyP8Fns1m+KFU9SgqoDl2mpLe18vL+hQ= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260826_053641_733930_F37372B2 X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Rockchip RK3576 features five MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 (not supported) - MIPI1: connected to MIPI DPHY0 - MIPI2: connected to MIPI DPHY0 lanes 2-3 in split mode (not supported) - MIPI3: connected to MIPI DPHY1 - MIPI4: connected to MIPI DPHY1 lanes 2-3 in split mode (not supported) The PHY to receiver routing is fixed. Only the full/split mode of each DPHY is selectable, via SYS_GRF_SOC_CON5 bits 1 and 2, whose reset value selects full mode, so no software configuration is required. As the MIPI DCPHY as well as the split DPHY mode are not yet supported, add only the device tree nodes for the MIPI1 and MIPI3 units. Signed-off-by: Amin Gattout --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index b7a527614243..cbf8b70cc15a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1324,6 +1324,58 @@ vdec_mmu: iommu@27b00800 { #iommu-cells = <0>; }; + csi1: csi@27c90000 { + compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0x27c90000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_1>; + phys = <&csi_dphy0>; + power-domains = <&power RK3576_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_in: port@0 { + reg = <0>; + }; + + csi1_out: port@1 { + reg = <1>; + }; + }; + }; + + csi3: csi@27cb0000 { + compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0x27cb0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_3>; + phys = <&csi_dphy1>; + power-domains = <&power RK3576_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_in: port@0 { + reg = <0>; + }; + + csi3_out: port@1 { + reg = <1>; + }; + }; + }; + vop: vop@27d00000 { compatible = "rockchip,rk3576-vop"; reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; -- 2.43.0