From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44B53C61DCB for ; Fri, 28 Aug 2026 15:08:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GNZHlfu6UdzNKO0+8Q56ktHvv/VBnO/DXQ93lde3I+s=; b=s13XQj/plP3jhFFwZPVti6Ma8U UPZjtOiw7JmLtdwXuuyxtKiSnQ5icNIwdPUzVnpipke+oTrTqSUTn/XK4H5Ay+OC/CLzgm3xNM8Cy HYFF8hai9CEQIuZYPfGlfWowDvxwhiYfGJtVLGrLc3jbThp3LdkW+X+REhAbSWmmlqjMDFhc2eYwM ei0+T5ZAOGYlO3JMCs6eH/ogCetbfu3NcYDW2rzHnHOcCTGMKNpfTpA4k+zY2NH0FRubJ0+xc8xb8 59UXMEZYJc8PslsDB2H2Tc0n4jKbH6pnr+tX6yFjvF2eVa+PrRTcNcduoiQlgtRsen+SfOo7vMjWg fXKyDqOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzyBg-000000063Wy-08Nd; Fri, 28 Aug 2026 15:08:12 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wzyBf-000000063Wb-0Rg1; Fri, 28 Aug 2026 15:08:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=GNZHlfu6UdzNKO0+8Q56ktHvv/VBnO/DXQ93lde3I+s=; b=q/dyyboqY/UmFNUABXblQzRene TK/DVA93hukWLf9bosAHsUnd574X/fnC4bGooH2vk4fRZLEI9KNk2nFWMNJHYcjdYRkIhTONUmnwp quRctJg56aHIIo7BY1aBC8JCnfFSrKvJXbiMbNkN7iHouwaN0io+S4krSQnw/vzHT1Klx1rGI3rHE aq6cN+si+oOdC1dgJOV1rkkmwD5rMsLJMEn3uQRjq1mHhlV+n+MflUGCIxGevO/WC6lOnq3BsR3xZ ePtEmuDoBXZQpkfgru/zTrRb+RU0bt/X6vEqiPAShudZO57H39JlJfry/OSaqdr0bRoD5uQfB3SPr B3Qjdz/w==; Received: from [2a00:f820:417:0:178:251:229:89] (helo=mx.nabladev.com) by desiato.infradead.org with esmtps (Exim 4.99.2 #2 (Red Hat Linux)) id 1wzyBb-00000008LYj-1iOA; Fri, 28 Aug 2026 15:08:10 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E964011D0F6; Fri, 28 Aug 2026 17:07:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787929673; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=GNZHlfu6UdzNKO0+8Q56ktHvv/VBnO/DXQ93lde3I+s=; b=b4fRGr4W9rKlID6TvUMhron9/HbgsTDywTVgNhqOrAL391exHc4iMAeyR2kkse94ajeCrL BqotSoJqXdIGT7TTu74HSbSlIXrZQ1X0zjEfYwGxVqzIzr0d0ZjQtZOvz02szB3NKEItDf QY8hvzf6QF2/ad4G6VkSS8YqwH6wm158WXHzEUuHCZN5fEigxWwNszVAvixFh52XU3Cg+P T+2nmtdsj6D8ZaDp4nyRLcdRJIAC5MRkzWzTUcwmv9PD+xFf2nSs0NSG2mZB9c0Hydk3J+ 6mexZdMX+XtdqMxAvPgRk2DiARaJ2/SU4mxxQ5Ammh8hVxDoErsZ9V1uMNiBlA== From: Marek Vasut To: linux-phy@lists.infradead.org Cc: Pankaj Dev , Rahul Kumar , Fabrice Gasnier , Christian Bruel , Marek Vasut , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Manivannan Sadhasivam , Maxime Coquelin , Neil Armstrong , Patrice Chotard , Rob Herring , Rosen Penev , Vinod Koul , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 2/2] phy: stm32: Add support for ST STM32MP25 USB2-FEMTO PHY Date: Fri, 28 Aug 2026 17:06:57 +0200 Message-ID: <20260828150739.174460-2-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828150739.174460-1-marex@nabladev.com> References: <20260828150739.174460-1-marex@nabladev.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260828_160807_701986_1A063548 X-CRM114-Status: GOOD ( 24.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pankaj Dev Add USB2 PHY driver for STM32MP25 USB2 controllers, which includes the USB2.0 host-only controller and USB 2.0 part of the DWC3 controller. Two such PHYs in total are present in STM32MP25 SoC, they both are slightly different, therefore they use different compatible string to discern them. Signed-off-by: Pankaj Dev Co-developed-by: Rahul Kumar Signed-off-by: Rahul Kumar Co-developed-by: Fabrice Gasnier Signed-off-by: Fabrice Gasnier Co-developed-by: Christian Bruel Signed-off-by: Christian Bruel Co-developed-by: Marek Vasut Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Christian Bruel Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Krzysztof Kozlowski Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Neil Armstrong Cc: Pankaj Dev Cc: Patrice Chotard Cc: Rahul Kumar Cc: Rob Herring Cc: Rosen Penev Cc: Vinod Koul Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com --- V2: - Fix up Sob/Cdb lines - Operate PHY as a syscon subnode V3: - Update copyright years - Register two sets of clock, one 480 MHz PLL and one CMN - Split PHY ops per PHY, since the PHY2 does not have set mode ops - Fix up Sob/Cdb lines further V4: - Split this from series arm64: dts: phy: st: usb: Add STM32MP2 USB support https://lore.kernel.org/all/20260822074816.548662-1-marex@nabladev.com/ --- drivers/phy/st/Kconfig | 10 + drivers/phy/st/Makefile | 1 + drivers/phy/st/phy-stm32-usb2phy.c | 406 +++++++++++++++++++++++++++++ 3 files changed, 417 insertions(+) create mode 100644 drivers/phy/st/phy-stm32-usb2phy.c diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index 49206185e5633..2835bb67bca9e 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -58,3 +58,13 @@ config PHY_STM32_USBPHYC used by an HS USB Host controller, and the second one is shared between an HS USB OTG controller and an HS USB Host controller, selected by a USB switch. + +config PHY_STM32_USB2PHY + tristate "STMicroelectronics STM32MP25 USB2.0 PHY Controller driver" + depends on ARCH_STM32 || COMPILE_TEST + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the High-Speed USB 2.0 transceivers that are + part of the STMicroelectronics STM32MP25 SoCs. The PHY itself is a + Synopsys FEMTO-PHY. diff --git a/drivers/phy/st/Makefile b/drivers/phy/st/Makefile index cb80e954ea9f0..4945df5ed78a8 100644 --- a/drivers/phy/st/Makefile +++ b/drivers/phy/st/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o obj-$(CONFIG_PHY_STM32_COMBOPHY) += phy-stm32-combophy.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o +obj-$(CONFIG_PHY_STM32_USB2PHY) += phy-stm32-usb2phy.o diff --git a/drivers/phy/st/phy-stm32-usb2phy.c b/drivers/phy/st/phy-stm32-usb2phy.c new file mode 100644 index 0000000000000..8c68b2d208d73 --- /dev/null +++ b/drivers/phy/st/phy-stm32-usb2phy.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32 USB2 PHY Controller driver + * Currently Only supported for STM32MP25 + * + * Copyright (C) 2022-2026 STMicroelectronics + * Author(s): Pankaj Dev . + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG_USB2PHY2CR_USB2PHY2CMN BIT(2) +#define SYSCFG_USB2PHY2CR_VBUSVALID BIT(4) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL BIT(5) +#define SYSCFG_USB2PHY2CR_VBUSVLDEXT BIT(6) + +#define USBH_NUM_CLK 2 + +struct stm32_usb2phy { + struct phy *phy; + struct regmap *regmap; + struct device *dev; + struct reset_control *rstc; + struct clk *phyref; + struct regulator *vdd33; + const struct stm32mp2_usb2phy_hw_data *hw_data; + atomic_t en_refcnt; + enum phy_mode mode; + u32 cr_offset; + bool is_init; + struct clk_hw clkpll_hw; + struct clk_hw clkcmn_hw; + /* Must be last */ + struct clk_hw_onecell_data onecell; +}; + +struct stm32mp2_usb2phy_hw_data { + u32 phyrefsel_mask; + const struct phy_ops *phy_ops; +}; + +static int stm32_usb2phy_enable(struct stm32_usb2phy *phy_dev) +{ + const struct stm32mp2_usb2phy_hw_data *phy_data = phy_dev->hw_data; + unsigned int refsel; + unsigned long rate; + int ret; + + /* Check if a phy is already init or clkpll in use */ + if (atomic_inc_return(&phy_dev->en_refcnt) > 1) + return 0; + + rate = clk_get_rate(phy_dev->phyref); + if (rate == 19200000) + refsel = 0; + else if (rate == 20000000) + refsel = 1; + else if (rate == 24000000) + refsel = 2; + else + return -EINVAL; + + ret = regmap_update_bits(phy_dev->regmap, + phy_dev->cr_offset, + phy_data->phyrefsel_mask, + field_prep(phy_data->phyrefsel_mask, refsel)); + if (ret) + return ret; + + ret = regulator_enable(phy_dev->vdd33); + if (ret) + return ret; + + ret = clk_prepare_enable(phy_dev->phyref); + if (ret) + goto error_regdis; + + ret = reset_control_deassert(phy_dev->rstc); + if (ret) + goto error_clkdis; + + return 0; + +error_clkdis: + clk_disable_unprepare(phy_dev->phyref); +error_regdis: + regulator_disable(phy_dev->vdd33); + + return ret; +} + +static int stm32_usb2phy_disable(struct stm32_usb2phy *phy_dev) +{ + int ret; + + /* Check if a phy is still init or clkpll in use */ + if (atomic_dec_return(&phy_dev->en_refcnt) > 0) + return 0; + + ret = reset_control_assert(phy_dev->rstc); + if (ret) + return ret; + + clk_disable_unprepare(phy_dev->phyref); + + return regulator_disable(phy_dev->vdd33); +} + +static int stm32_usb2phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct stm32_usb2phy *phy_dev = phy_get_drvdata(phy); + u32 mask = SYSCFG_USB2PHY2CR_USB2PHY2CMN | + SYSCFG_USB2PHY2CR_VBUSVALID | + SYSCFG_USB2PHY2CR_VBUSVLDEXT; + u32 val = 0; + int ret; + + if (mode == PHY_MODE_USB_HOST) { + if (submode != USB_ROLE_NONE) + val = SYSCFG_USB2PHY2CR_VBUSVALID; + } else if (mode == PHY_MODE_USB_DEVICE) { + val = SYSCFG_USB2PHY2CR_USB2PHY2CMN | + SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL; + if (submode != USB_ROLE_NONE) + val |= SYSCFG_USB2PHY2CR_VBUSVLDEXT; + mask |= SYSCFG_USB2PHY2CR_VBUSVLDEXTSEL; + } else { + return -EINVAL; + } + + ret = regmap_update_bits(phy_dev->regmap, phy_dev->cr_offset, mask, val); + if (ret) + return ret; + + phy_dev->mode = mode; + + return 0; +} + +static int stm32_usb2phy1_init(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev = phy_get_drvdata(phy); + int ret; + + ret = stm32_usb2phy_enable(phy_dev); + if (ret) + return ret; + + phy_dev->is_init = true; + + return 0; +} + +static int stm32_usb2phy2_init(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev = phy_get_drvdata(phy); + int ret; + + ret = stm32_usb2phy_enable(phy_dev); + if (ret) + return ret; + + if (phy_dev->mode != PHY_MODE_INVALID) { + ret = stm32_usb2phy_set_mode(phy, phy_dev->mode, USB_ROLE_NONE); + if (ret) { + stm32_usb2phy_disable(phy_dev); + return ret; + } + } + + phy_dev->is_init = true; + + return 0; +} + +static int stm32_usb2phy_exit(struct phy *phy) +{ + struct stm32_usb2phy *phy_dev = phy_get_drvdata(phy); + int ret; + + ret = stm32_usb2phy_disable(phy_dev); + if (ret) + return ret; + + phy_dev->is_init = false; + + return 0; +} + +static const struct phy_ops stm32_usb2phy1_data = { + .init = stm32_usb2phy1_init, + .exit = stm32_usb2phy_exit, + .owner = THIS_MODULE, +}; + +static const struct phy_ops stm32_usb2phy2_data = { + .init = stm32_usb2phy2_init, + .exit = stm32_usb2phy_exit, + .set_mode = stm32_usb2phy_set_mode, + .owner = THIS_MODULE, +}; + +static int stm32_usb2phy_clkpll_prepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev = container_of(hw, struct stm32_usb2phy, + clkpll_hw); + + return stm32_usb2phy_enable(phy_dev); +} + +static void stm32_usb2phy_clkpll_unprepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev = container_of(hw, struct stm32_usb2phy, + clkpll_hw); + + stm32_usb2phy_disable(phy_dev); +} + +static unsigned long stm32_usb2phy_clkpll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return 480000000; +} + +static const struct clk_ops stm32_usb2phy_clkpll_ops = { + .prepare = stm32_usb2phy_clkpll_prepare, + .unprepare = stm32_usb2phy_clkpll_unprepare, + .recalc_rate = stm32_usb2phy_clkpll_recalc_rate, +}; + +static int stm32_usb2phy_clkcmn_prepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev = container_of(hw, struct stm32_usb2phy, + clkcmn_hw); + + return regmap_clear_bits(phy_dev->regmap, phy_dev->cr_offset, + SYSCFG_USB2PHY2CR_USB2PHY2CMN); +} + +static void stm32_usb2phy_clkcmn_unprepare(struct clk_hw *hw) +{ + struct stm32_usb2phy *phy_dev = container_of(hw, struct stm32_usb2phy, + clkcmn_hw); + + regmap_set_bits(phy_dev->regmap, phy_dev->cr_offset, + SYSCFG_USB2PHY2CR_USB2PHY2CMN); +} + +static const struct clk_ops stm32_usb2phy_clkcmn_ops = { + .prepare = stm32_usb2phy_clkcmn_prepare, + .unprepare = stm32_usb2phy_clkcmn_unprepare, +}; + +static int stm32_usb2phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct stm32_usb2phy *phy_dev; + char *pllname, *cmnname; + const __be32 *offset; + struct phy *phy; + int ret; + + phy_dev = devm_kzalloc(dev, struct_size(phy_dev, onecell.hws, USBH_NUM_CLK), GFP_KERNEL); + if (!phy_dev) + return -ENOMEM; + + phy_dev->dev = dev; + dev_set_drvdata(dev, phy_dev); + + phy_dev->rstc = devm_reset_control_get(dev, NULL); + if (IS_ERR(phy_dev->rstc)) + return dev_err_probe(dev, PTR_ERR(phy_dev->rstc), "Failed to get USB2PHY reset\n"); + + phy_dev->phyref = devm_clk_get(dev, NULL); + if (IS_ERR(phy_dev->phyref)) + return dev_err_probe(dev, PTR_ERR(phy_dev->phyref), "Failed to get phyref clk\n"); + + phy_dev->vdd33 = devm_regulator_get_optional(dev, "vdd33"); + if (IS_ERR(phy_dev->vdd33)) + return dev_err_probe(dev, PTR_ERR(phy_dev->vdd33), "Failed to get vdd3v3 supply\n"); + + phy_dev->regmap = syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(phy_dev->regmap)) + return dev_err_probe(dev, PTR_ERR(phy_dev->regmap), "Failed to get regmap\n"); + + offset = of_get_address(dev->of_node, 0, NULL, NULL); + if (!offset) + return dev_err_probe(dev, -EINVAL, "Failed to get regmap offset\n"); + + phy_dev->cr_offset = be32_to_cpu(*offset); + + phy_dev->hw_data = device_get_match_data(dev); + + phy = devm_phy_create(dev, NULL, phy_dev->hw_data->phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Failed to create PHY\n"); + + phy_dev->phy = phy; + phy_set_drvdata(phy, phy_dev); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + pllname = devm_kasprintf(dev, GFP_KERNEL, "clk_%s_48m", + of_node_full_name(dev->of_node)); + if (!pllname) + return -ENOMEM; + + cmnname = devm_kasprintf(dev, GFP_KERNEL, "clk_%s_cmn", + of_node_full_name(dev->of_node)); + if (!cmnname) + return -ENOMEM; + + phy_dev->onecell.num = USBH_NUM_CLK; + phy_dev->onecell.hws[0] = &phy_dev->clkpll_hw; + phy_dev->onecell.hws[1] = &phy_dev->clkcmn_hw; + + phy_dev->clkpll_hw.init = CLK_HW_INIT_NO_PARENT(pllname, &stm32_usb2phy_clkpll_ops, 0); + ret = devm_clk_hw_register(phy_dev->dev, &phy_dev->clkpll_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to register PLL clock\n"); + + phy_dev->clkcmn_hw.init = CLK_HW_INIT_HW(cmnname, &phy_dev->clkpll_hw, + &stm32_usb2phy_clkcmn_ops, 0); + ret = devm_clk_hw_register(phy_dev->dev, &phy_dev->clkcmn_hw); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to register CMN clock\n"); + + ret = devm_of_clk_add_hw_provider(phy_dev->dev, of_clk_hw_onecell_get, &phy_dev->onecell); + if (ret) + return dev_err_probe(phy_dev->dev, ret, "Failed to add clock provider\n"); + + return 0; +} + +static int stm32_usb2phy_suspend(struct device *dev) +{ + struct stm32_usb2phy *phy_dev = dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_disable(phy_dev); + + return 0; +} + +static int stm32_usb2phy_resume(struct device *dev) +{ + struct stm32_usb2phy *phy_dev = dev_get_drvdata(dev); + + if (phy_dev->is_init) + return stm32_usb2phy_enable(phy_dev); + + return 0; +} + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 Host controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy1_hwdata = { + .phyrefsel_mask = GENMASK(6, 4), + .phy_ops = &stm32_usb2phy1_data, +}; + +/* STM32MP25xx USB 2.0 PHY attached to USB 2.0 part of DWC3 controller */ +static const struct stm32mp2_usb2phy_hw_data stm32mp25_usb2phy2_hwdata = { + .phyrefsel_mask = GENMASK(14, 12), + .phy_ops = &stm32_usb2phy2_data, +}; + +static const struct of_device_id stm32_usb2phy_of_match[] = { + { .compatible = "st,stm32mp25-usb2phy1", .data = &stm32mp25_usb2phy1_hwdata }, + { .compatible = "st,stm32mp25-usb2phy2", .data = &stm32mp25_usb2phy2_hwdata }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, stm32_usb2phy_of_match); + +static DEFINE_SIMPLE_DEV_PM_OPS(stm32_usb2phy_pm_ops, + stm32_usb2phy_suspend, stm32_usb2phy_resume); + +static struct platform_driver stm32_usb2phy_driver = { + .probe = stm32_usb2phy_probe, + .driver = { + .name = "stm32-usb2phy", + .of_match_table = stm32_usb2phy_of_match, + .pm = pm_sleep_ptr(&stm32_usb2phy_pm_ops) + } +}; + +module_platform_driver(stm32_usb2phy_driver); + +MODULE_AUTHOR("Pankaj Dev "); +MODULE_DESCRIPTION("STMicroelectronics Generic USB2PHY driver for stm32"); +MODULE_LICENSE("GPL"); -- 2.53.0