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Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Michal Simek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King CC: , , , Subject: [PATCH net-next v3 2/6] dt-bindings: net: xlnx,xxv-ethernet: Add Xilinx XXV 10G/25G Ethernet Date: Mon, 31 Aug 2026 20:38:12 +0530 Message-ID: <20260831150816.1020883-3-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260831150816.1020883-1-suraj.gupta2@amd.com> References: <20260831150816.1020883-1-suraj.gupta2@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EF:EE_|BN7PPFA8145BD40:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c895dcc-b62f-4778-370a-08df0771c2f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|23010399003|36860700016|13003099007|921020|3023799007|56012099006|10067099003|22082099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: alebvt4q02tvjRjNMUoLOBk1hwdRdhg71bteeCb1UMOtaSGgUPfkKfGLhq/UmbgDae8S4iuIAwld2kpjoQDcvG9WDQJyAvFj7EQ7insNo7N1fz/50xbxHOS97iqkDi/stC6gPFaOw+EWe9tS2z/RcLPvuti8leaYLKz1ZTkft/NVRzuXagFRuF8KKeYin71kjXIMTkLNy+ICG65uet25/XeYoJDRiSnPHhx7dV5rGceqY0bUbPfUViCtJ5da8ODHb7zggj8d/zJWz3AuyH/zFEi9VNKCSteGxeRBvHX6jggJoKYKuQfzgq38jF1vFVuGvVjMlekk58NZq/law9DMUwo4LIgEQl0U/WVx5zscU9Ov4xF9WI1fHKcxbMNM6aP5AqAyuk/YPpVph5U4UG6PqCxqadqn1RuMVtZJD4q9EtFKCd6YX/XAxR0a1BduGzjumFPSWyuZKaoMrtb1WRa4vjHSJIHjNJEh5N8FOqmcjoMlQmdu3kekflO7pKntocPX56aWlaL7HxBVEn1RwtDI7a5UAf3nZLd+Cjeqo6a5CSDbsN/ma0oxagTds8qLjcAZwZcKbPoxlXrGn9XKoRZfYyyyb1QKudad28ByQy6XJ3NhZIiqCpFg2+3mBKu8OuiRCEVExrNSCVeMtiqFLy4up0GFzWFdr+KjsQDunJ23vCIYQ6NTV3b8dCvOiPne2+DWto/cPqQ7Absw0w9X0m6q6w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(23010399003)(36860700016)(13003099007)(921020)(3023799007)(56012099006)(10067099003)(22082099003)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wETLs0F1nPKEH4vTJIz68h8msWCPRjtdgkwH5oXHF4/anp//6ZOFoK9Jf1Ilfow5jaq+hKhrlC4eEGqSZ56g6HZPJ8s1YjEyZH/Ch3rrsaGHniykLsSG8TMO4hIeGCF4dqQhqRvEQAx4QqFtAyiK+E+uylJbu4UmWW7LgZQSorKJVMPgQyNXvWY8YCuCQaSwN7xlQX7KvEWmWR6szexg6e7g4BNeXUndkLuNpemfcXv7MH0kb6OiVzPGBnDcb2SOs4lOXjczkOzTEpGNES7k8EeC+YOS4z6wpyn4ibuTK/0/l7HiTh2NWU1It6j4/fMw2GT0UUiQaoJ5ofWyv+ipu6f72EUvb6mlxYLhwcTJaAJ76zVXgsBgGCsyY58/FCPpZeA1QAMZr+PdrMrYUrpn1G09/mJZ02/vU154kM+CGKQ5QR6yTTssKQmKwKBuFXic X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2026 15:08:49.2357 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c895dcc-b62f-4778-370a-08df0771c2f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPFA8145BD40 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_160858_907450_55013FF5 X-CRM114-Status: GOOD ( 17.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The XXV Ethernet IP integrates a 10G/25G Ethernet MAC with an in-core PCS/PMA driving a high-speed serial transceiver. Its payload is moved by an external AXI DMA (or multichannel DMA) controller referenced through the dmas/dma-names properties. Document the IP in a dedicated schema file. Add the "xlnx,xxv-ethernet-1.0" compatible with the 10gbase-r and 25gbase-r phy-modes, the rx_core/drp/s_axi clocks and the AXI DMA channel properties. Signed-off-by: Suraj Gupta Reviewed-by: Rob Herring (Arm) --- .../bindings/net/xlnx,xxv-ethernet.yaml | 107 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml diff --git a/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml new file mode 100644 index 000000000000..2be3ade11d46 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/xlnx,xxv-ethernet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx XXV 10G/25G Ethernet Subsystem + +maintainers: + - Radhey Shyam Pandey + - Suraj Gupta + +description: + The Xilinx XXV Ethernet Subsystem implements a 10G/25G Ethernet MAC with an + in-core PCS/PMA driving a high-speed serial transceiver. It supports the + 10GBASE-R and 25GBASE-R line rates, with 25G operation following the 25G + Ethernet Consortium specification. It has no external MDIO PHY, and its + payload is moved by an external AXI DMA (or multichannel DMA) controller + referenced through the "dmas" property. + +properties: + compatible: + const: xlnx,xxv-ethernet-1.0 + + reg: + maxItems: 1 + description: MAC control and status register space. + + clocks: + items: + - description: RX AXI4-Stream clock. + - description: GT DRP clock. + - description: AXI4-Lite register clock. + + clock-names: + items: + - const: rx_core + - const: drp + - const: s_axi + + phy-mode: + enum: + - 10gbase-r + - 25gbase-r + + xlnx,rxmem: + description: + Size in bytes of the Rx/Tx packet buffer memory built into the IP. It is + fixed by the hardware design and bounds the largest frame (jumbo MTU) the + device can accept. + $ref: /schemas/types.yaml#/definitions/uint32 + + dmas: + minItems: 2 + maxItems: 32 + description: TX and RX DMA channel phandle. + + dma-names: + items: + pattern: "^[tr]x_chan([0-9]|1[0-5])$" + description: + Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel and + "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel. + minItems: 2 + maxItems: 32 + +required: + - compatible + - reg + - clocks + - clock-names + - phy-mode + - xlnx,rxmem + - dmas + - dma-names + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + +unevaluatedProperties: false + +examples: + # Single AXI DMA channel pair + - | + ethernet@80000000 { + compatible = "xlnx,xxv-ethernet-1.0"; + reg = <0x80000000 0x10000>; + clock-names = "rx_core", "drp", "s_axi"; + clocks = <&rx_clk>, <&drp_clk>, <&axi_clk>; + dma-names = "tx_chan0", "rx_chan0"; + dmas = <&axi_dma 0>, <&axi_dma 1>; + phy-mode = "25gbase-r"; + xlnx,rxmem = <0x8000>; + }; + # Multichannel DMA (MCDMA) with multiple Tx/Rx channels + - | + ethernet@80010000 { + compatible = "xlnx,xxv-ethernet-1.0"; + reg = <0x80010000 0x10000>; + clock-names = "rx_core", "drp", "s_axi"; + clocks = <&rx_clk>, <&drp_clk>, <&axi_clk>; + dma-names = "tx_chan0", "tx_chan1", "rx_chan0", "rx_chan1"; + dmas = <&axi_mcdma 0>, <&axi_mcdma 1>, + <&axi_mcdma 16>, <&axi_mcdma 17>; + phy-mode = "10gbase-r"; + xlnx,rxmem = <0x8000>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2d420d40782e..8160a8ddec65 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -29557,6 +29557,7 @@ XILINX AXI ETHERNET DRIVER M: Radhey Shyam Pandey S: Maintained F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +F: Documentation/devicetree/bindings/net/xlnx,xxv-ethernet.yaml F: drivers/net/ethernet/xilinx/xilinx_axienet* XILINX CAN DRIVER -- 2.25.1