From: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
To: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Chen-Yu Tsai <wenst@chromium.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Edward-JW Yang <edward-jw.yang@mediatek.com>
Cc: kernel@collabora.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Subject: [PATCH v6 16/27] clk: mediatek: Move fhctl_parse_dt call into mtk_clk_register_pllfhs
Date: Fri, 04 Sep 2026 17:58:27 +0200 [thread overview]
Message-ID: <20260904-mt8189-clocks-system-base-v6-16-5df247f56938@collabora.com> (raw)
In-Reply-To: <20260904-mt8189-clocks-system-base-v6-0-5df247f56938@collabora.com>
Currently, in the probe functions of apmixedsys drivers with PLL
frequency hopping support (FHCTL), the call to mtk_clk_register_pllfh
is always preceded by a call to fhctl_parse_dt.
This function purpose is to prepare FHCTL-related internal data, that
are then used by mtk_clk_register_pllfhs. It is not used in another
case and both functions are implemented in the same source file
(clk-pllfh.c). There is little interest to keep as it this call
sequence in the several probe functions.
So, add an additional parameter (compatible name string) in
mtk_clk_register_pllfhs and move the fhctl_parse_dt call into it.
Finally, make this function private by removing it from clk-pllfh.h
include, remove its EXPORT_SYMBOL_GPL macro use and add the static
keyword.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 3 +--
drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 5 ++---
drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 4 +---
drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 4 +---
drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 4 +---
drivers/clk/mediatek/clk-pllfh.c | 10 ++++++----
drivers/clk/mediatek/clk-pllfh.h | 5 +----
7 files changed, 13 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
index 123d5d7fea85..a860708ef908 100644
--- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c
@@ -151,8 +151,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- ret = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls),
+ ret = mtk_clk_register_pllfhs(dev, fhctl_node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (ret)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
index d7d416172ab3..8920eb1c3fa6 100644
--- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
@@ -156,9 +156,8 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
goto unmap_io;
}
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
- r = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs,
- ARRAY_SIZE(pllfhs), clk_data);
+ r = mtk_clk_register_pllfhs(dev, fhctl_node, plls, ARRAY_SIZE(plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
index d35dd2632e43..e8fc6bd90fcb 100644
--- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
@@ -149,9 +149,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-
- r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
+ r = mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
index b0563a285bd6..2e4f5aff9eee 100644
--- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c
@@ -160,9 +160,7 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-
- r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
+ r = mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
index a120c3305547..12e51b39b764 100644
--- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
@@ -178,9 +178,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
- fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-
- r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
+ r = mtk_clk_register_pllfhs(&pdev->dev, fhctl_node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c
index f36dbc7fa06d..398edad2a69e 100644
--- a/drivers/clk/mediatek/clk-pllfh.c
+++ b/drivers/clk/mediatek/clk-pllfh.c
@@ -69,8 +69,9 @@ static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs,
return NULL;
}
-void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
- int num_fhs)
+static void fhctl_parse_dt(const u8 *compatible_node,
+ struct mtk_pllfh_data *pllfhs,
+ int num_fhs)
{
void __iomem *base;
struct device_node *node;
@@ -121,7 +122,6 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
iounmap(base);
goto out_node_put;
}
-EXPORT_SYMBOL_GPL(fhctl_parse_dt);
static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
{
@@ -252,7 +252,7 @@ static void mtk_clk_cleanup_pllfhs(void __iomem *iomem_base,
}
-int mtk_clk_register_pllfhs(struct device *dev,
+int mtk_clk_register_pllfhs(struct device *dev, const u8 *fhctl_node,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
@@ -261,6 +261,8 @@ int mtk_clk_register_pllfhs(struct device *dev,
int i;
struct clk_hw *hw;
+ fhctl_parse_dt(fhctl_node, pllfhs, num_fhs);
+
base = of_iomap(dev->of_node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h
index a9eb7558de1c..07269e467e34 100644
--- a/drivers/clk/mediatek/clk-pllfh.h
+++ b/drivers/clk/mediatek/clk-pllfh.h
@@ -71,7 +71,7 @@ struct fh_operation {
extern const struct clk_ops mtk_pllfh_setclr_ops;
-int mtk_clk_register_pllfhs(struct device *dev,
+int mtk_clk_register_pllfhs(struct device *dev, const u8 *fhctl_node,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_pllfhs,
struct clk_hw_onecell_data *clk_data);
@@ -80,7 +80,4 @@ void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data);
-void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
- int num_pllfhs);
-
#endif /* __CLK_PLLFH_H */
--
2.55.0
next prev parent reply other threads:[~2026-09-04 15:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 15:58 [PATCH v6 00/27] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 01/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 02/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8192 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 03/27] dt-bindings: clock: mediatek: Make '#clock-cells' required for MT8195 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 04/27] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 05/27] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 06/27] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 07/27] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 08/27] dt-bindings: clock: mediatek: Add MT8189 system/base clocks and resets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 09/27] clk: mediatek: Harmonize mtk_pll_fenc related symbol names Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 10/27] clk: mediatek: pll: Add BAR reset register offsets Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 11/27] clk: mediatek: pll: Factorise pll power on/off sequences Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 12/27] clk: mediatek: pll: Add PLL stabilization delay definition Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 13/27] clk: mediatek: pll: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 14/27] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 15/27] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs Louis-Alexis Eyraud
2026-09-04 15:58 ` Louis-Alexis Eyraud [this message]
2026-09-04 15:58 ` [PATCH v6 17/27] clk: mediatek: pllfh: clear state data in mtk_clk_cleanup_pllfhs Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 18/27] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 19/27] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 20/27] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 21/27] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 22/27] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 23/27] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 24/27] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 25/27] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 26/27] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-09-04 15:58 ` [PATCH v6 27/27] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
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