From: Hemanth Selam <hemanth.selam@gmail.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/4] arm64: fix typos in comments
Date: Fri, 4 Sep 2026 16:21:08 +0530 [thread overview]
Message-ID: <20260904105114.29474-3-hemanth.selam@gmail.com> (raw)
In-Reply-To: <20260904105114.29474-1-hemanth.selam@gmail.com>
Fix typos in comments, reported by scripts/checkpatch.pl using the
misspelling list in scripts/spelling.txt. Only touches comments, no code
changes.
Assisted-by: Cursor:claude-opus-5
Signed-off-by: Hemanth Selam <hemanth.selam@gmail.com>
---
arch/arm64/include/asm/stage2_pgtable.h | 2 +-
arch/arm64/include/uapi/asm/ptrace.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h
index 23d27623e478..cf57da90b5d1 100644
--- a/arch/arm64/include/asm/stage2_pgtable.h
+++ b/arch/arm64/include/asm/stage2_pgtable.h
@@ -17,7 +17,7 @@
*
* This implies, the total number of page table levels required for
* IPA_SHIFT at stage2 expected by the hardware can be calculated using
- * the same logic used for the (non-collapsable) stage1 page tables but for
+ * the same logic used for the (non-collapsible) stage1 page tables but for
* (IPA_SHIFT - 4).
*/
#define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4)
diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
index 15649a253a57..0c8c6a126c3b 100644
--- a/arch/arm64/include/uapi/asm/ptrace.h
+++ b/arch/arm64/include/uapi/asm/ptrace.h
@@ -113,7 +113,7 @@ struct user_hwdebug_state {
struct user_sve_header {
__u32 size; /* total meaningful regset content in bytes */
- __u32 max_size; /* maxmium possible size for this thread */
+ __u32 max_size; /* maximum possible size for this thread */
__u16 vl; /* current vector length */
__u16 max_vl; /* maximum possible vector length */
__u16 flags;
@@ -272,7 +272,7 @@ struct user_pac_generic_keys {
struct user_za_header {
__u32 size; /* total meaningful regset content in bytes */
- __u32 max_size; /* maxmium possible size for this thread */
+ __u32 max_size; /* maximum possible size for this thread */
__u16 vl; /* current vector length */
__u16 max_vl; /* maximum possible vector length */
__u16 flags;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 17b83a2518a8..fd52941b5f07 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -888,7 +888,7 @@ static int search_cmp_ftr_reg(const void *id, const void *regp)
* entry.
*
* returns - Upon success, matching ftr_reg entry for id.
- * - NULL on failure. It is upto the caller to decide
+ * - NULL on failure. It is up to the caller to decide
* the impact of a failure.
*/
static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
@@ -3682,7 +3682,7 @@ static void verify_local_cpu_caps(u16 scope_mask)
/*
* We have to issue cpu_enable() irrespective of
* whether the CPU has it or not, as it is enabeld
- * system wide. It is upto the call back to take
+ * system wide. It is up to the call back to take
* appropriate action on this CPU.
*/
if (caps->cpu_enable)
--
2.48.1
next prev parent reply other threads:[~2026-09-04 10:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260904105114.29474-1-hemanth.selam@gmail.com>
2026-09-04 10:51 ` [PATCH 1/4] Documentation/arch: fix typo "initalised" in comment Hemanth Selam
2026-09-04 22:01 ` Randy Dunlap
2026-09-04 10:51 ` Hemanth Selam [this message]
2026-09-04 10:51 ` [PATCH 3/4] selftests: arm64: fix typo "hander" " Hemanth Selam
2026-09-04 10:51 ` [PATCH 4/4] arm64: include: fix repeated word 'to' " Hemanth Selam
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