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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EKAVq6yqAiVENJsEdwAEuboOUBWhF93+lPtflUQ4aB/QeuQi4kxntn8vyzzLkS61u8QljpYrxE8447mG0iAd15o3ItfNBDS7U1BsRQUTVbjcl8iSFKk/WWsZJQfqlK3DLKsS6IEH7Hbydfo8uW6D4BpFHNKLWCra6gHT6Rp9yFdfri1wtsW1laMrzxnmzHI+x1rKYBT8BEknxe6sfX24cpI8ZacA7MjHeVnYgq69pFEtujwSmhLgZzJDh47XZgLD1u8dNlPViSsjzpZacjPAnEMdYcvs0AYj39V3upM7Ao/U+P+fYZfkwCDWnRpjNj6AIlgLR3zHLz5EVxyhYEa4VB/9LjxpBtnzDTpzJVJ/uE+Nt1ej4ghSL7vNR5DG05Jkr7efFq0dpfK9gCRG8Yj1uYaJDEgGvZsMKd9ELIFb89lshA5UUQa4AFwS0VVBY7Ke X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2026 11:42:59.3352 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b264c3ed-b84f-4ed1-e488-08df0a79ab7d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000099.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB9255 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_044305_277713_FD085C96 X-CRM114-Status: GOOD ( 21.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When a GICv5 VPE is made non-resident as part of the vcpu entering WFI, request a VPE doorbell so that KVM can be notified when a suitable SPI or LPI becomes pending for that VPE. Program the doorbell priority mask, DBPM, from the effective virtual priority mask before making the VPE non-resident. DBPM is the priority threshold used by the GICv5 hardware to decide whether a pending SPI or LPI is allowed to signal the VPE doorbell. This allows hardware to signal the doorbell only for interrupts that the vcpu can actually take, and avoids waking it for interrupts masked by the guest priority state. If no interrupt can be signalled to the vcpu, leave the doorbell request clear. Attempt to make the doorbell interrupt affine to the current CPU before requesting it. Treat affinity failures as non-fatal and continue using the existing placement. A successful move nudges the wakeup back towards the CPU that last ran the vcpu, where the relevant state is more likely to be cache-hot, while also spreading doorbell interrupts across host PEs as different vcpus enter WFI on different CPUs. Clear stale db_fired state before making the VPE non-resident. Any previous doorbell notification has already been consumed by this point, and clearing it before the non-resident transition ensures that a newly fired doorbell is observed. Finally, teach kvm_vgic_vcpu_pending_irq() to report pending work for a GICv5 vcpu when its VPE doorbell has fired, in addition to the existing pending-PPI check. Signed-off-by: Sascha Bischoff --- arch/arm64/kvm/hyp/vgic-v5-sr.c | 9 +++++++ arch/arm64/kvm/vgic/vgic-v5.c | 46 +++++++++++++++++++++++++++++++++ arch/arm64/kvm/vgic/vgic.c | 6 ++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/hyp/vgic-v5-sr.c b/arch/arm64/kvm/hyp/vgic-v5-s= r.c index f064045a31aee..46992a6c2cacb 100644 --- a/arch/arm64/kvm/hyp/vgic-v5-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v5-sr.c @@ -22,6 +22,15 @@ void __vgic_v5_make_resident(struct vgic_v5_cpu_if *cpu_= if) =20 void __vgic_v5_make_non_resident(struct vgic_v5_cpu_if *cpu_if) { + /* + * Clear the db_fired state to ensure that we're ready for the next + * doorbell when it is requested. If a doorbell firing caused us to + * enter the guest, then we've already consumed that state at this + * point, so this is safe to clear. Use WRITE_ONCE() to ensure we're not + * racing with the doorbell firing and setting the state true again. + */ + WRITE_ONCE(cpu_if->gicv5_vpe.db_fired, false); + /* * Make as non-resident before actually making non-resident. Avoids race * with doorbell arriving. diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index d7d6db5014269..5a058ef8fe701 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -1095,6 +1095,52 @@ void vgic_v5_put(struct kvm_vcpu *vcpu) kvm_call_hyp(__vgic_v5_save_apr, cpu_if); =20 cpu_if->vgic_contextr =3D 0; + if (vcpu_get_flag(vcpu, IN_WFI)) { + u32 priority_mask; + int dbpm; + + /* + * Find the virtual running priority and use this to calculate + * the doorbell priority mask. We combine the highest active + * priority and the CPU's priority mask. The guest can't handle + * interrupts with priorities less than or equal to the virtual + * running priority, so there's literally no point in waking the + * guest for these. + * + * The priority needs to be higher than the mask to signal, so + * pick the next higher priority (subtract 1). + */ + priority_mask =3D vgic_v5_get_effective_priority_mask(vcpu); + + /* + * Request a doorbell *unless* the priority is 0, indicating + * that no interrupt can wake the CPU up. + */ + if (priority_mask) { + int db_irq =3D vgic_v5_vpe_db(vcpu); + struct irq_data *d =3D irq_get_irq_data(db_irq); + const struct cpumask *aff =3D irq_data_get_effective_affinity_mask(d); + int cpu =3D smp_processor_id(); + + dbpm =3D priority_mask - 1; + cpu_if->vgic_contextr =3D FIELD_PREP(ICH_CONTEXTR_EL2_DB, 1) | + FIELD_PREP(ICH_CONTEXTR_EL2_DBPM, dbpm); + + /* + * Make the doorbell affine to this CPU, if it isn't + * already. Actively check the cpumask first as it is + * cheaper than changing the affinity every time. + */ + if (!cpumask_test_cpu(cpu, aff)) { + int ret; + + ret =3D irq_set_affinity(db_irq, cpumask_of(cpu)); + if (ret) + kvm_debug_ratelimited("Failed to move doorbell IRQ %d to CPU %d: %d\n= ", + db_irq, cpu, ret); + } + } + } =20 kvm_call_hyp(__vgic_v5_make_non_resident, cpu_if); =20 diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c index b25303d9919fd..ca4fb45f7d501 100644 --- a/arch/arm64/kvm/vgic/vgic.c +++ b/arch/arm64/kvm/vgic/vgic.c @@ -1236,8 +1236,12 @@ int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) unsigned long flags; struct vgic_vmcr vmcr; =20 - if (vgic_is_v5(vcpu->kvm)) + if (vgic_is_v5(vcpu->kvm)) { + if (READ_ONCE(vcpu->arch.vgic_cpu.vgic_v5.gicv5_vpe.db_fired)) + return true; + return vgic_v5_has_pending_ppi(vcpu); + } =20 if (!vcpu->kvm->arch.vgic.enabled) return false; --=20 2.34.1