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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r7QtP7UNqmDWU4O8zFO9radpRwMKCOrEEkp849bcCAbpp4mIb1UvE7ULHgjNuqpEy7d0x9m6znbXOmTc47XUsT1fiGc83O+7q3vm4BRMRj2mIHPZX8J4/5AHqxJ4F/XbIn3MUjbgfSCteisPXLk2+DnXPEd1d/elDIvu45W41hYp4T32BbNEASz7qBo8Bi4DqlxbBNztHgjZdMdT7rFNJNZg8HEe9KYHRFMpHBhAwfMvp89t7ziDDZSAmMqiRwVgUKl2ufAUpKb/umNhZRSp9vw93B6tx3hW/4IvVezFeiNDs++qQ88NsBiiFvQIqMSvqALvDd+7QzX10pPzAVlh6UOZpBgO39C0SYH3EneV7d7tRnyBoUyxWhK3VOySf5ZKoew7glGT/BKHhjuGR7+1RiIJD/lepWBdXFCojGzH5MrydpyXiLdE6yE3eNCa4ZS5 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2026 11:38:22.8376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b97aae9-3b09-412c-9ee8-08df0a7906af X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A61.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7747 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_043829_565635_04503BB6 X-CRM114-Status: GOOD ( 16.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM needs access to the host IRS configuration frame to configure virtual-machine resources. The frame ID registers describe the capabilities available to KVM. Cache IRS_IDR2, IRS_IDR3, and IRS_IDR4 rather than extracting their individual fields into kvm_vgic_global_state. Accessor helpers derive the required capabilities from the cached registers. Use the cached IRS_IDR4 VPE capacity to limit the maximum number of vCPUs, while retaining VGIC_V5_MAX_CPUS as KVM's own upper bound. Keeping the raw register values lets KVM adjust the exposed capabilities when needed, as is done for ICH_VTR_EL2, and avoids tying future EL2 code to the layout of kvm_vgic_global_state. Signed-off-by: Sascha Bischoff --- arch/arm64/kvm/vgic/vgic-v5.c | 22 +++++++++- include/kvm/arm_vgic.h | 75 +++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index 4e3e4db24e773..e75a66b3920aa 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -11,6 +11,7 @@ #include "vgic.h" =20 #define ppi_caps kvm_vgic_global_state.vgic_v5_ppi_caps +#define irs_caps kvm_vgic_global_state.vgic_v5_irs_caps =20 /* * Not all PPIs are guaranteed to be implemented for GICv5. Deterermine wh= ich @@ -34,6 +35,21 @@ static void vgic_v5_get_implemented_ppis(void) __assign_bit(GICV5_ARCH_PPI_PMUIRQ, ppi_caps.impl_ppi_mask, system_suppor= ts_pmuv3()); } =20 +static u32 irs_readl_relaxed(const u32 reg_offset) +{ + return readl_relaxed(irs_caps.irs_base + reg_offset); +} + +static void vgic_v5_irs_cache_id_regs(const struct gic_kvm_info *info) +{ + irs_caps.irs_base =3D info->gicv5_irs.base; + irs_caps.non_coherent =3D info->gicv5_irs.non_coherent; + + irs_caps.idr2 =3D irs_readl_relaxed(GICV5_IRS_IDR2); + irs_caps.idr3 =3D irs_readl_relaxed(GICV5_IRS_IDR3); + irs_caps.idr4 =3D irs_readl_relaxed(GICV5_IRS_IDR4); +} + /* * Probe for a vGICv5 compatible interrupt controller, returning 0 on succ= ess. */ @@ -60,10 +76,12 @@ int vgic_v5_probe(const struct gic_kvm_info *info) goto skip_v5; } =20 - kvm_vgic_global_state.max_gic_vcpus =3D VGIC_V5_MAX_CPUS; - + vgic_v5_irs_cache_id_regs(info); vgic_v5_get_implemented_ppis(); =20 + kvm_vgic_global_state.max_gic_vcpus =3D min(vgic_v5_irs_max_vpes(&irs_cap= s), + VGIC_V5_MAX_CPUS); + ret =3D kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V5); if (ret) { kvm_err("Cannot register GICv5 KVM device.\n"); diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 086b7578e5f33..c82aa7c9e3f32 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -132,6 +132,19 @@ enum vgic_type { VGIC_V5, /* Newer, fancier GICv5 */ }; =20 +struct vgic_v5_irs_caps { + /* Base address of the host IRS's CONFIG_FRAME */ + void __iomem *irs_base; + + /* Raw host IRS ID registers */ + u32 idr2; + u32 idr3; + u32 idr4; + + /* Is the IRS coherent with us, or not? */ + bool non_coherent; +}; + /* same for all guests, as depending only on the _host's_ GIC model */ struct vgic_global { /* type of the host GIC */ @@ -182,6 +195,9 @@ struct vgic_global { struct { DECLARE_BITMAP(impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS); } vgic_v5_ppi_caps; + + /* GICv5 IRS capabilities */ + struct vgic_v5_irs_caps vgic_v5_irs_caps; }; =20 extern struct vgic_global kvm_vgic_global_state; @@ -627,6 +643,65 @@ int vgic_v4_load(struct kvm_vcpu *vcpu); void vgic_v4_commit(struct kvm_vcpu *vcpu); int vgic_v4_put(struct kvm_vcpu *vcpu); =20 +static inline u8 vgic_v5_irs_ist_id_bits(const struct vgic_v5_irs_caps *ca= ps) +{ + return FIELD_GET(GICV5_IRS_IDR2_ID_BITS, caps->idr2); +} + +static inline u8 vgic_v5_irs_min_lpi_id_bits(const struct vgic_v5_irs_caps= *caps) +{ + return FIELD_GET(GICV5_IRS_IDR2_MIN_LPI_ID_BITS, caps->idr2); +} + +static inline bool vgic_v5_irs_ist_levels(const struct vgic_v5_irs_caps *c= aps) +{ + return !!(caps->idr2 & GICV5_IRS_IDR2_IST_LEVELS); +} + +static inline u8 vgic_v5_irs_ist_l2sz(const struct vgic_v5_irs_caps *caps) +{ + return FIELD_GET(GICV5_IRS_IDR2_IST_L2SZ, caps->idr2); +} + +static inline bool vgic_v5_irs_istmd(const struct vgic_v5_irs_caps *caps) +{ + return !!(caps->idr2 & GICV5_IRS_IDR2_ISTMD); +} + +static inline u8 vgic_v5_irs_istmd_sz(const struct vgic_v5_irs_caps *caps) +{ + return FIELD_GET(GICV5_IRS_IDR2_ISTMD_SZ, caps->idr2); +} + +static inline u32 vgic_v5_irs_max_vms(const struct vgic_v5_irs_caps *caps) +{ + return BIT(FIELD_GET(GICV5_IRS_IDR3_VM_ID_BITS, caps->idr3)); +} + +static inline bool vgic_v5_irs_two_level_vmt_support(const struct vgic_v5_= irs_caps *caps) +{ + return !!(caps->idr3 & GICV5_IRS_IDR3_VMT_LEVELS); +} + +static inline u16 vgic_v5_irs_vmd_size(const struct vgic_v5_irs_caps *caps= ) +{ + if (!(caps->idr3 & GICV5_IRS_IDR3_VMD)) + return 0; + + return BIT(FIELD_GET(GICV5_IRS_IDR3_VMD_SZ, caps->idr3)); +} + +static inline u16 vgic_v5_irs_vped_size(const struct vgic_v5_irs_caps *cap= s) +{ + return BIT(FIELD_GET(GICV5_IRS_IDR4_VPED_SZ, caps->idr4)); +} + +static inline u32 vgic_v5_irs_max_vpes(const struct vgic_v5_irs_caps *caps= ) +{ + /* Field stores VPE_ID_BITS - 1 */ + return BIT(FIELD_GET(GICV5_IRS_IDR4_VPE_ID_BITS, caps->idr4) + 1); +} + int vgic_v5_finalize_ppi_state(struct kvm *kvm); bool vgic_v5_ppi_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq, unsigned long flags); --=20 2.34.1