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Sun, 6 Sep 2026 03:24:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CF.mail.protection.outlook.com (10.167.240.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Sun, 6 Sep 2026 03:24:33 +0000 Received: from hongliang-System-Product-Name (unknown [172.20.64.180]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 780EB409210D; Sun, 6 Sep 2026 11:24:32 +0800 (CST) From: Hongliang Yang To: peter.chen@kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, gregkh@linuxfoundation.org, krzk@kernel.org Subject: [PATCH v4 1/3] dt-bindings: phy: Add CIX Sky1 USB3 PHY Date: Sun, 6 Sep 2026 11:24:29 +0800 Message-ID: <20260906032431.470744-2-hongliang.yang@cixtech.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260906032431.470744-1-hongliang.yang@cixtech.com> References: <20260906032431.470744-1-hongliang.yang@cixtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CF:EE_|TYZPR06MB7255:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: bb820fb4-f32f-48f1-2083-08df0bc65f1b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|36860700016|1800799024|82310400026|376014|10067099003|3023799007|22082099003|18002099003|56012099006|921020; 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Signed-off-by: Hongliang Yang --- .../bindings/phy/cix,sky1-usb3-phy.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml new file mode 100644 index 000000000000..5b025a48c844 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cix,sky1-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 USB3 PHY + +maintainers: + - Hongliang Yang + +description: + The CIX Sky1 USB3 PHY is a multi-port SuperSpeedPlus PHY that + supports up to two USB3 lanes. Each port is represented as a + child node of the PHY controller. + +properties: + compatible: + const: cix,sky1-usb3-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: APB register interface clock + - description: PHY reference clock + + clock-names: + items: + - const: apb + - const: ref + + resets: + items: + - description: PHY reset + - description: PHY APB preset + + reset-names: + items: + - const: core + - const: apb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^usb-port@[0-9a-f]+$": + type: object + description: + A single USB3 PHY port/lane. + + properties: + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + usb-phy@9210000 { + compatible = "cix,sky1-usb3-phy"; + reg = <0x9210000 0x40000>; + #address-cells = <1>; + clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>, + <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>; + clock-names = "apb", "ref"; + resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>, + <&s5_syscon SKY1_USBPHY_SS_PST_N>; + reset-names = "core", "apb"; + #size-cells = <0>; + + usb-port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb-port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; -- 2.54.0