Re: [PATCH v5 4/9] iommu/arm-smmu-v3: Optimize range invalidation for latency

[Jason Gunthorpe <jgg@nvidia.com>]

On Mon, Sep 07, 2026 at 12:23:05PM -0300, Jason Gunthorpe wrote:
> > > -			/* Determine how many chunks of 2^scale size we have */
> > > -			num = (num_pages >> scale) & CMDQ_TLBI_RANGE_NUM_MAX;
> > > -
> > > -			/* Keep the pre-DS 5-bit truncation when scale > 31 */
> > > -			cmd->data[0] = orig_data0 |
> > > -				FIELD_PREP(CMDQ_TLBI_0_NUM, num - 1) |
> > > -				FIELD_PREP(CMDQ_TLBI_0_SCALE, scale & 0x1f);
> > 
> > That just deletes the DS code which was recently merged.
> > I see that is added again in the last patch, but it would make more
> > sense to do it in the same patch I guess.
> 
> I missed it when rebasing, I'll adjust it

Actually it is correct like this. The earlier commit 773f2b9e3670
("iommu/arm-smmu-v3: Support IDR5.DS and widen the TLBI SCALE field")
did not actually support a wider scale it just widened the field and
added this protective truncate.

So this commit still does not support a wider scale and we don't need
the protective truncate because this version directly limits scale's
value.

The later patch truely is the one to add proper DS support and it
doesn't bring back the "& 0x1f", it adjusts the new code that limited
scale.

Jason