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From: Linkai Gong <gonglinkai@kylinos.cn>
To: Michal Simek <michal.simek@amd.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Mike Turquette <mturquette@linaro.org>,
	Soren Brinkmann <soren.brinkmann@xilinx.com>,
	Kees Cook <kees@kernel.org>,
	Babanpreet Singh <bbnpreetsingh@gmail.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, gonglinkai@kylinos.cn
Subject: Re: [PATCH] clk: zynq: return -ETIMEDOUT if the PLL never locks
Date: Tue,  8 Sep 2026 16:44:13 +0800	[thread overview]
Message-ID: <20260908084413.1503572-1-gonglinkai@kylinos.cn> (raw)
In-Reply-To: <6eec3c2f-5fa2-4e8c-a9a5-82b01cc0a8dc@amd.com>

On Mon, Sep 07, 2026 at 02:58:18PM +0200, Michal Simek wrote:
> BIT(clk->lockbit)
>
> And 10 and 1000 are magic values.
>
> Fix itself is fine but I would prefer to explain more why 1ms upper limit was
> used. I don't think it is going to be a problem and 10-1000us is fine. I just
> want to make sure that it will be clear that this value is not coming from any
> TRM but still at least range is aligned with expectation in HW.

Thanks for the review.

Agreed on both points. v2 will use BIT(), name the poll delay/timeout,
and clarify in the commit message that 1 ms is a software upper bound
for a stuck PLL under spinlock, not a TRM-derived value; lock is still
expected well within that window on Zynq.

Will send v2 shortly.

Thanks,
Linkai


  reply	other threads:[~2026-09-08  8:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-01 12:53 [PATCH] clk: zynq: return -ETIMEDOUT if the PLL never locks Linkai Gong
2026-09-07 12:58 ` Michal Simek
2026-09-08  8:44   ` Linkai Gong [this message]
2026-09-08  8:47 ` [PATCH v2] " Linkai Gong

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