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([39.170.101.209]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39d770bc9f5sm4442434a91.2.2026.09.10.01.10.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2026 01:10:27 -0700 (PDT) From: Zxyan Zhu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, richardcochran@gmail.com, maxime.chevallier@bootlin.com, muhammad.nazim.amirul.nazle.asmade@altera.com, rohan.g.thomas@altera.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Zxyan Zhu Subject: [PATCH net-next v5 0/2] net: stmmac: dwxgmac2: timestamp interrupt support + Agilex5 fix Date: Thu, 10 Sep 2026 16:10:18 +0800 Message-Id: <20260910081020.86227-1-zxyan0222@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260910_011030_551619_BFD3EFF2 X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds auxiliary snapshot (EXTTS) interrupt support to DWXGMAC2/DWXLGMAC2 and fixes a stale TSIS race on the Agilex5 cross-timestamp path that the new handler would otherwise expose. Patch 1 makes smtg_crosststamp() complete on the persistent ATSNS count instead of the transient TSIS bit, waits for the ATSFC FIFO clear to complete before arming, and derives the pop count from the poll result, so the completion condition is immune to the destructive reads of XGMAC_TIMESTAMP_STATUS performed by the DWXGMAC2 timestamp interrupt handler and the TX timestamp completion path. Patch 2 wires up a dedicated DWXGMAC2 timestamp interrupt handler. Before this change the XGMAC hwif entries used the generic stmmac_ptp ops, whose timestamp_interrupt callback read the dwmac4 offset GMAC_TIMESTAMP_STATUS (0xb20) instead of the XGMAC register at 0xd20, and XGMAC_TSIE was never enabled, so auxiliary snapshot events were never reported on XGMAC platforms. Because v5 changes the completion mechanism, the previous Tested-by for the mask approach no longer applies; Patch 1 needs re-verification on Agilex5 hardware. v1: https://lore.kernel.org/netdev/20260806-dwxgmac2-timestamp-irq-v1-1-c051c79c9d90@gmail.com/ v2: https://lore.kernel.org/netdev/20260810100221.9166-1-zxyan0222@gmail.com/ v3: https://lore.kernel.org/netdev/20260818132722.1852876-1-zxyan0222@gmail.com/ v4: https://lore.kernel.org/netdev/20260902131441.322167-1-zxyan0222@gmail.com/ v5: - Replace the XGMAC_TSIE masking approach with completing the cross-timestamp on the persistent ATSNS count, and reorder the series so it is bisect-safe. - Wait for the ATSFC FIFO clear to complete before arming, so a stale ATSNS count from a previous snapshot cannot be observed. Zxyan Zhu (2): net: stmmac: dwmac-socfpga: complete cross-timestamp on ATSNS net: stmmac: dwxgmac2: add XGMAC timestamp interrupt support .../ethernet/stmicro/stmmac/dwmac-socfpga.c | 29 ++++++++++--- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 +- .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 43 +++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/hwif.c | 4 +- drivers/net/ethernet/stmicro/stmmac/hwif.h | 1 + .../ethernet/stmicro/stmmac/stmmac_hwtstamp.c | 12 ++++++ .../net/ethernet/stmicro/stmmac/stmmac_ptp.h | 1 + 7 files changed, 84 insertions(+), 8 deletions(-) -- 2.34.1