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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4842546a51bsm836569fac.0.2026.09.15.12.03.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 12:03:37 -0700 (PDT) From: James Hilliard Date: Tue, 15 Sep 2026 13:03:19 -0600 Subject: [PATCH net-next 2/2] net: stmmac: sun8i: add support for Allwinner H616 EMAC1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260915-submit-h616-emac1-v1-v1-2-195de0bb1f8a@gmail.com> References: <20260915-submit-h616-emac1-v1-v1-0-195de0bb1f8a@gmail.com> In-Reply-To: <20260915-submit-h616-emac1-v1-v1-0-195de0bb1f8a@gmail.com> To: Richard Genoud , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin Cc: Maxime Ripard , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, James Hilliard X-Mailer: b4 0.15.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_121128_806828_B60FC616 X-CRM114-Status: GOOD ( 13.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The H616 secondary EMAC uses a separate system-control clock register and supports only RMII at 10/100 Mbps. Its EPHY is provided by a companion AC200 or AC300 package rather than an internal PHY block. Add an EMAC1 variant using the dedicated register and mark the PHY as external. The register retains the standard five-bit RX and three-bit TX clock delay chains, so expose their supported ranges to the shared syscon setup. Co-developed-by: Richard Genoud Signed-off-by: Richard Genoud Signed-off-by: James Hilliard --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 48c52eb96233..fdc0c3384af8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -81,6 +81,13 @@ static const struct reg_field sun8i_syscon_reg_field = { .msb = 31, }; +/* EMAC1 clock register @ 0x34 in the "system control" address range */ +static const struct reg_field sun8i_syscon_reg_field_emac1 = { + .reg = 0x34, + .lsb = 0, + .msb = 31, +}; + /* EMAC clock register @ 0x164 in the CCU address range */ static const struct reg_field sun8i_ccu_reg_field = { .reg = 0x164, @@ -143,6 +150,18 @@ static const struct emac_variant emac_variant_h6 = { .tx_delay_max = 7, }; +static const struct emac_variant emac_variant_h616_emac1 = { + .syscon_field = &sun8i_syscon_reg_field_emac1, + /* + * The "internal PHY" is in a companion AC200 or AC300 package, + * rather than on the H616 die. + */ + .soc_has_internal_phy = false, + .support_rmii = true, + .rx_delay_max = 31, + .tx_delay_max = 7, +}; + #define EMAC_BASIC_CTL0 0x00 #define EMAC_BASIC_CTL1 0x04 #define EMAC_INT_STA 0x08 @@ -1278,6 +1297,8 @@ static const struct of_device_id sun8i_dwmac_match[] = { .data = &emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", .data = &emac_variant_h6 }, + { .compatible = "allwinner,sun50i-h616-emac1", + .data = &emac_variant_h616_emac1 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); -- 2.53.0