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Tue, 15 Sep 2026 16:19:06 -0700 (PDT) X-Received: by 2002:a17:90b:398d:b0:39d:ec1f:b3fd with SMTP id 98e67ed59e1d1-39dfe036be1mr8656394a91.8.1789514346415; Tue, 15 Sep 2026 16:19:06 -0700 (PDT) Received: from localhost ([50.35.44.179]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bf5a6a175sm2279027eec.9.2026.09.15.16.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 16:19:06 -0700 (PDT) Date: Tue, 15 Sep 2026 16:19:02 -0700 From: Jonathan Cameron To: Nicolin Chen Cc: , , , , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: Re: [PATCH v5 03/15] iommu/arm-smmu-v3: Add Q_POS() macro Message-ID: <20260915161902.00006cd1@oss.qualcomm.com> In-Reply-To: <1db9d32df4a59dcac286e7a82bc2704cdd69b8e0.1789446520.git.nicolinc@nvidia.com> References: <1db9d32df4a59dcac286e7a82bc2704cdd69b8e0.1789446520.git.nicolinc@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BdVNQbt2 c=1 sm=1 tr=0 ts=6aa9d26b cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=aNnz9XPx1a4JIXSYt2cE/A==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=Ikd4Dj_1AAAA:8 a=EUspDBNiAAAA:8 a=39RnTaQb96y4xN-8A7QA:9 a=CjuIK1q_8ugA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDM0MSBTYWx0ZWRfX0Wx5nkSewzuC ymA7VvvhCMPfUMJade1lbRfb35mQkRHxTqnHOSG4VuGojn6NPvs9TKQ9v1ts7PHrvsN6LHZIjNs mKNBf6ONRKavOT9ZnbUFOv7xqIZfaaq0TvaxpXTLytCb/duF2avJTS2D626VMNSZxLPIGfOm2PE cKpIzGPCE0/Gd7/EODtDrHzPc+iwfqH+uGspIPy5ST3E1Td+vI2cZ+NMcuGc+82HddcWU8eOEYp t6XZUBoEw/CrL9uxleT5PWHPN/5AcbMWVlS470kDXM0OF0SKoVw3o8tpGgIyXqDTrjyMQr4v3CU 65YQRIH2A3kMPB6AZ2YLgkQ0jF14fQL8KUDG8hO2pBZ9wBCMOc+Nttu+HB5RF4om9sUHMckQdwe nQ7vZ6Vhf5YCVFF04o4NvRId66JuOA4CgvAnCwO5CbuZeDPQzgDlbK6rLLkk/A2XQSGylVJywLd XcodZ028PQAhPOTQIbA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDM0MSBTYWx0ZWRfX8S3pTjCmJXXn qHSYmlvqojhWWTbxYezZQe63GjuIsghSCpl9O8Qmhh40YaALB8DaE9vfy/khUE2NURLG5dBlYJ6 gLG/yT/Qi9axSh8B+IeWnO6yR+3bC0o= X-Proofpoint-GUID: JteyjtTxKC_arlCsmCmkw8jrxg64UKfX X-Proofpoint-ORIG-GUID: JteyjtTxKC_arlCsmCmkw8jrxg64UKfX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150341 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_161908_567955_C9650E94 X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 15 Sep 2026 09:38:15 -0700 Nicolin Chen wrote: > A queue position, the wrap bit combined with the index, is Q_WRP | Q_IDX. > It is a (max_n_shift + 1)-bit value that wraps at twice the queue capacity. > queue_inc_cons(), queue_sync_cons_ovf(), and queue_inc_prod_n() currently > compute such positions by open-coding the two macros at each call site. > > Add a Q_POS() macro and switch the open-coded sites to it. > > A subsequent change will build a Q_DIFF() on it, to count the entries that > a queue pointer moved past. > > No functional change intended. > > Assisted-by: LLM > Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron