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(unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wDnbxQduKpqGzAlBA--.54876S4; Wed, 16 Sep 2026 23:39:12 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com>, Mahesh Vaidya , Ricardo Pardini , Shawn Lin Subject: [PATCH v9 2/3] PCI: Configure Root Port MPS during host probing Date: Wed, 16 Sep 2026 23:39:06 +0800 Message-Id: <20260916153907.60344-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260916153907.60344-1-18255117159@163.com> References: <20260916153907.60344-1-18255117159@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: _____wDnbxQduKpqGzAlBA--.54876S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxJF4fJF15AF47uFWUuw4UArb_yoW5GrWkpa yUWanYyFs7GF4fZFsrZ3WFvFyYqF93Zry3GrZ3Z3s0van8Zr9rJrWaya95Jw1kGrZ7KFya vFn8try8u3ZIvFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEVyIbUUUUU= X-Originating-IP: [240e:b8f:91b3:d000:a95a:12fc:887a:b0f1] X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAB7H2qquCBtpwAA3y X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260916_084000_997506_A4A86371 X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Current PCIe initialization logic may leave Root Ports operating with non-optimal Maximum Payload Size (MPS) settings. The existing code in pci_configure_mps() returns early for devices without an upstream bridge which includes Root Ports, so their MPS values remain at firmware defaults. This fails to utilize the controller's full capabilities, leading to suboptimal data transfer efficiency across the PCIe hierarchy. With this patch, during the host controller probing phase: - When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF) and not PCIE_BUS_PEER2PEER (which requires the default 128 bytes for optimal peer-to-peer operation), and - The device is a Root Port, the Root Port's MPS is set to its maximum supported value. Note that this initial maximum MPS setting may be reduced later, during downstream device enumeration, if any downstream device does not support the Root Port's maximum MPS. This change ensures Root Ports are initialized to their maximum MPS before downstream devices negotiate MPS, while maintaining backward compatibility via the PCIE_BUS_TUNE_OFF check and not interfering with the PCIE_BUS_PEER2PEER strategy. Suggested-by: Niklas Cassel Suggested-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam Signed-off-by: Hans Zhang <18255117159@163.com> Tested-by: Mahesh Vaidya Tested-by: Ricardo Pardini # on Odroid-HC4 Tested-by: Shawn Lin --- drivers/pci/probe.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 232bce2819f0..08af75aa7366 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2248,6 +2248,21 @@ static void pci_configure_mps(struct pci_dev *dev) return; } + /* + * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all) or + * PCIE_BUS_PEER2PEER (use minimum MPS for peer-to-peer), set Root Ports' + * MPS to their maximum supported value. Depending on the MPS strategy + * and MPSS of downstream devices, a Root Port's MPS may be reduced + * later during device enumeration. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && + pcie_bus_config != PCIE_BUS_TUNE_OFF && + pcie_bus_config != PCIE_BUS_PEER2PEER) { + rc = pcie_set_mps(dev, 128 << dev->pcie_mpss); + if (rc) + dev_warn(&dev->dev, "failed to set root port MPS\n"); + } + if (!bridge || !pci_is_pcie(bridge)) return; -- 2.34.1