From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA0F4C982DC for ; Fri, 18 Sep 2026 11:34:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iDeJRo4bih/KSuJdrKkaN4r0lNb81DygeGh2CLqTayQ=; b=4NxTjZk/QOt/yJoeVJ1lyK4oQb eXUWISGn5gko+9P45oIw4hwdcKbJoWAub1YXNWA5HZPzc+//mG+xFizA/iJl0VSeWmuyMQ89jLYmi hmFY0BmVh8LaLHHL0fanzgF/8ybJ8TZqYfmIbstRig6HKgdbfxQUn6tk7kA2UfhChY48pd/aX2VNP uSxTaVozDTrjRSKPls3f2eZeggCGcm3V1X0cynQvuQj1vZxX7ia98XTZDxPIKyvoeP5mb3FO0ifz+ X3oQ3WpJrCVA1MT+HE4yvkEyPfNxxrcfmJG4h0+HuHA5+TQHdQ58+Eb2uZJgXKBc1g/ZSSdvHxMQM NGroxNPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x7WrX-0000000EEjR-1K3y; Fri, 18 Sep 2026 11:34:39 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1x7WrN-0000000EEfR-00KB for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2026 11:34:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1789731269; x=1821267269; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=QYGrFqOkLMGg0egcUveRB4ur4cCoutEpPPiq+t5aHao=; b=czJpfBZVfjw8WLOJzPySXIcBfhq/mUtHKqiyt7X/2ledVQB/HXyLAmzm HIcBNilW7E2WnRct2lRf7dDzxP7xb7sXWkUUeTil5n3xOcpghE85t+ysr OWvAmkZnhMJ1LQmLB+Usa9+H3wzpM1YFMC6zkK+EuVFivk6cukHUxJone Z5gTXwY2zFKJYJHyX7YhGgw5khzDdnrA30eUhFIpY1R5zlBfQtdYHxDE+ ob39kxxGbHnL+CMy0piB6q/fTh8htVnRzLrTKs/CxgPizReSKYaXfctBZ Q9ESKPayWF2iJMKr1jn8o/KohDcnvOhaaqWZ7mjJ39GVG8bpYKVFeCAJ1 Q==; X-CSE-ConnectionGUID: uo6KZvGdTLa58gFarbPKYA== X-CSE-MsgGUID: U1RNkHnpQXi54m3bcOSe6Q== X-IronPort-AV: E=Sophos;i="6.27,108,1787036400"; d="scan'208";a="295223728" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2026 04:34:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Fri, 18 Sep 2026 04:34:27 -0700 Received: from DEN-DL-M70577.microsemi.net (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 18 Sep 2026 04:34:23 -0700 From: Daniel Machon Date: Fri, 18 Sep 2026 13:33:56 +0200 Subject: [PATCH net-next v7 04/14] net: lan966x: add FDMA LLP register write helper MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260918-lan966x-pci-fdma-v7-4-0ecc179c8a2c@microchip.com> References: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> In-Reply-To: <20260918-lan966x-pci-fdma-v7-0-0ecc179c8a2c@microchip.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Steen Hegelund , , "Alexei Starovoitov" , Daniel Borkmann , "Jesper Dangaard Brouer" , John Fastabend , Stanislav Fomichev , Herve Codina , Arnd Bergmann , Greg Kroah-Hartman , Mohsin Bashir CC: Richard Cochran , , , , X-Mailer: b4 0.14.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260918_043429_060469_8F06232E X-CRM114-Status: GOOD ( 13.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The FDMA Link List Pointer (LLP) register points to the first DCB in the chain and must be written before the channel is activated. This tells the FDMA engine where to begin DMA transfers. Move the LLP register writes from the channel start/activate functions into the allocation functions and introduce a shared lan966x_fdma_llp_configure() helper. This is needed because the upcoming PCIe FDMA path writes ATU-translated addresses to the LLP registers instead of DMA addresses. Keeping the writes in the shared start/activate path would overwrite these translated addresses. Tested-by: Herve Codina Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/lan966x/lan966x_fdma.c | 30 ++++++++++------------ 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c index 41d4ec7f2f57..b8344fd5e5ad 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_fdma.c @@ -109,6 +109,13 @@ static int lan966x_fdma_rx_alloc_page_pool(struct lan966x_rx *rx) return 0; } +static void lan966x_fdma_llp_configure(struct lan966x *lan966x, u64 addr, + u8 channel_id) +{ + lan_wr(lower_32_bits(addr), lan966x, FDMA_DCB_LLP(channel_id)); + lan_wr(upper_32_bits(addr), lan966x, FDMA_DCB_LLP1(channel_id)); +} + static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) { struct lan966x *lan966x = rx->lan966x; @@ -128,6 +135,8 @@ static int lan966x_fdma_rx_alloc(struct lan966x_rx *rx) fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), FDMA_DCB_STATUS_INTR); + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; } @@ -137,14 +146,6 @@ static void lan966x_fdma_rx_start(struct lan966x_rx *rx) struct fdma *fdma = &rx->fdma; u32 mask; - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -215,6 +216,8 @@ static int lan966x_fdma_tx_alloc(struct lan966x_tx *tx) fdma_dcbs_init(fdma, 0, 0); + lan966x_fdma_llp_configure(lan966x, fdma->dma, fdma->channel_id); + return 0; out: @@ -236,14 +239,6 @@ static void lan966x_fdma_tx_activate(struct lan966x_tx *tx) struct fdma *fdma = &tx->fdma; u32 mask; - /* When activating a channel, first is required to write the first DCB - * address and then to activate it - */ - lan_wr(lower_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP(fdma->channel_id)); - lan_wr(upper_32_bits((u64)fdma->dma), lan966x, - FDMA_DCB_LLP1(fdma->channel_id)); - lan_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) | FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(1) | FDMA_CH_CFG_CH_INJ_PORT_SET(0) | @@ -876,6 +871,9 @@ static int lan966x_fdma_reload(struct lan966x *lan966x, int new_mtu) MEM_TYPE_PAGE_POOL, page_pool); } + lan966x_fdma_llp_configure(lan966x, lan966x->rx.fdma.dma, + lan966x->rx.fdma.channel_id); + lan966x_fdma_rx_start(&lan966x->rx); lan966x_fdma_wakeup_netdev(lan966x); -- 2.34.1