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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e362e9402sm7969141a91.15.2026.09.17.20.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 20:01:32 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v7 0/7] drm/verisilicon: add Nuvoton MA35D1 DCU Lite support Date: Fri, 18 Sep 2026 11:01:18 +0800 Message-ID: <20260918030125.315978-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260917_200135_709665_5E3F42DE X-CRM114-Status: GOOD ( 21.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the Verisilicon DCUltraLite display controller as integrated in the Nuvoton MA35D1 SoC. The Verisilicon DC driver and its DT binding were originally written by Icenowy Zheng for the T-Head TH1520 SoC, which carries a DC8200 IP block. The present series builds on that foundation with gratitude to Icenowy for the original work. The DCUltraLite is a different variant in the DC IP family. While the two IPs share a broadly similar register layout, a number of differences prevent the existing driver from working on the MA35D1 without modification: - No CONFIG_EX commit path: the DC8200 staging registers (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG, PANEL_CONFIG_EX) are absent. The DCUltraLite uses enable (bit 0) and reset (bit 4) bits in FB_CONFIG for direct framebuffer updates, and requires a per-frame VALID bit toggle (FB_CONFIG bit 3) to latch configuration changes. - No PANEL_START register: panel output begins when PANEL_CONFIG.RUNNING is set; the DC8200 multi-display sync start register at 0x1CCC does not exist. - Different IRQ registers: DISP_IRQ_STA at 0x147C / DISP_IRQ_EN at 0x1480, versus the DC8200's TOP_IRQ_ACK at 0x0010 / TOP_IRQ_EN at 0x0014. - Simpler clock topology: the MA35D1 clock controller gates the core, AXI and AHB clocks with a single bit, so the devicetree supplies the same clock phandle for all three; only the pixel clock is distinct. No second output port is present, so no pix1 clock is needed either. - Single display output: no per-output indexing beyond index 0 is needed. - Hardware-discoverable identity: the DCUltraLite exposes chip identity registers whose model field reads 0x0 (revision 0x5560, customer_id 0x305), allowing the existing vs_fill_chip_identity() path to identify the variant purely through register reads. Patch 1 adds the nuvoton,ma35d1-dcu compatible to the verisilicon,dc DT binding and relaxes the top-level clock/reset item counts so per-variant allOf/if blocks can constrain each compatible's actual topology. Patch 2 adds the register-level macros needed by the DC8000 ops. Patches 3-4 introduce the driver changes in two logical steps: the vs_dc_funcs hardware ops vtable with DC8200 ops extracted into vs_dc8200.c, and the DC8000 ops in vs_dc8000.c. Patch 5 adds the DCUltraLite HWDB entry that gates hardware recognition once all support is in place. Patch 6 adds the Kconfig dependency on ARCH_MA35, placed last because it is only meaningful after the HWDB entry is added. Patch 7 fixes a pre-existing DC8200 bug in the primary plane disable path that Icenowy spotted while reviewing patch 3. All patches have been tested on Nuvoton MA35D1 hardware. Changes from v6: - [dt-bindings] Added a "port@1: false" / "required: port@0" restriction to the nuvoton,ma35d1-dcu allOf/if block, since the DCUltraLite only has a single output port. - [driver] Fixed 3 "alignment should match open parenthesis" checkpatch --strict issues introduced by patch 3: vs_crtc_atomic_begin() and vs_crtc_atomic_flush() continuation lines in vs_crtc.c, and vs_dc8200_primary_plane_update_ex()'s continuation line in vs_dc8200.c. - [driver] Added patch 7 to fix the pre-existing DC8200 FB_EN regmap_set_bits()/regmap_clear_bits() bug in vs_dc8200_primary_plane_disable_ex(), carried over unchanged since commit dbf21777caa8 ("drm: verisilicon: add a driver for Verisilicon display controllers"). Joey Lu (7): dt-bindings: display: verisilicon,dc: add support for nuvoton,ma35d1-dcu drm/verisilicon: add register-level macros for DC8000 drm/verisilicon: introduce per-variant hardware ops table drm/verisilicon: add DC8000 (DCUltraLite) display controller support drm/verisilicon: add DCUltraLite chip identity to HWDB drm/verisilicon: extend Kconfig to support ARCH_MA35 platforms drm/verisilicon: fix DC8200 primary plane disable clearing FB_EN .../bindings/display/verisilicon,dc.yaml | 51 ++++++++ drivers/gpu/drm/verisilicon/Kconfig | 2 +- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_bridge.c | 20 +-- drivers/gpu/drm/verisilicon/vs_crtc.c | 38 +++++- drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 1 + drivers/gpu/drm/verisilicon/vs_dc.c | 9 +- drivers/gpu/drm/verisilicon/vs_dc.h | 33 +++++ drivers/gpu/drm/verisilicon/vs_dc8000.c | 92 +++++++++++++ drivers/gpu/drm/verisilicon/vs_dc8200.c | 121 ++++++++++++++++++ drivers/gpu/drm/verisilicon/vs_drm.c | 5 +- drivers/gpu/drm/verisilicon/vs_drm.h | 8 ++ drivers/gpu/drm/verisilicon/vs_hwdb.c | 14 ++ drivers/gpu/drm/verisilicon/vs_hwdb.h | 6 + .../gpu/drm/verisilicon/vs_primary_plane.c | 32 +---- .../drm/verisilicon/vs_primary_plane_regs.h | 3 + 16 files changed, 382 insertions(+), 55 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8000.c create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8200.c -- 2.43.0