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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1790005161; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=GyqoFNSanEeBxdsQdbMl1XUDGrCiYm9GRKaNInNkFHs=; b=fpYtcEeHGUwSp/jOJ4aAP/3PJ2KSzPRT8ZIhwTuSYFfLe5n+u8aXDI94jqIPNX8a vABFzUzxpijELHM5WMfIqMsKJbhdyonm5WFW694di2mahFyJsSm83tCTqjtVgNNV9v+ IVN28+szHg3e40nixrbWv3qPjpmiKfsWkW/XFRYI= Received: by smtp.zohomail.com with SMTPS id 1790005158049450.6589859179186; Mon, 21 Sep 2026 08:39:18 -0700 (PDT) From: Junhui Liu Date: Mon, 21 Sep 2026 23:38:00 +0800 Subject: [PATCH v4 2/8] clk: sunxi-ng: sdm: Add dual patterns support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-a733-clk-v4-2-9c184ebe9ac1@pigmoral.tech> References: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> In-Reply-To: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5946; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=VJaKDsY2wNXh9jcfEAVgeUkR8XziO8+1SsD0dyIaS04=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLI2+udf9Njw0GvmhleVb/S/OZ379+Zh4Yxlz7dXGl91T T9vWxJyrqOUhUGMi0FWTJGFy1/8n7UOz7cjAq33YeawMoEMYeDiFICJ1Now/GbVs7n3cr/3nB6e hpRfDq0qTw7sS2D5aiZ8ovPD023bL2QzMswNdfDKEukzPbQg9cUTdy6ZmzrX5BmYP39W+j79grP 0Km4A X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_083946_512768_00F5A0C4 X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On newer Allwinner platforms like the A733, the Sigma-Delta Modulation (SDM) control logic is more complex. The SDM enable bit, which was previously located in the PLL register, is now moved to a second pattern register (PATTERN1). To support this, rename the existing "tuning" members to "pattern0" to align with the datasheet, and introduce the _SUNXI_CCU_SDM_DUAL_PAT macro to provide pattern1 register support. Related operations are also updated. Tested-by: Jerome Brunet Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu_sdm.c | 52 ++++++++++++++++++++++++++++++------------ drivers/clk/sunxi-ng/ccu_sdm.h | 29 ++++++++++++++--------- 2 files changed, 55 insertions(+), 26 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c index c564e5f9e610..7e13ffd246d3 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.c +++ b/drivers/clk/sunxi-ng/ccu_sdm.c @@ -18,7 +18,11 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common, if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) return false; - return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable); + if (sdm->pat1_enable && + (readl(common->base + sdm->pat1_reg) & sdm->pat1_enable) != sdm->pat1_enable) + return false; + + return !!(readl(common->base + sdm->pat0_reg) & sdm->pat0_enable); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, "SUNXI_CCU"); @@ -37,18 +41,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common, for (i = 0; i < sdm->table_size; i++) if (sdm->table[i].rate == rate) writel(sdm->table[i].pattern, - common->base + sdm->tuning_reg); + common->base + sdm->pat0_reg); /* Make sure SDM is enabled */ spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + sdm->tuning_reg); - writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); + writel(reg | sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); - spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + common->reg); - writel(reg | sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + common->reg); + writel(reg | sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + sdm->pat1_reg); + writel(reg | sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, "SUNXI_CCU"); @@ -61,14 +74,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common, if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD)) return; - spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + common->reg); - writel(reg & ~sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + common->reg); + writel(reg & ~sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + sdm->pat1_reg); + writel(reg & ~sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + sdm->tuning_reg); - writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); + writel(reg & ~sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, "SUNXI_CCU"); @@ -123,7 +145,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common, pr_debug("%s: clock is sigma-delta modulated\n", clk_hw_get_name(&common->hw)); - reg = readl(common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); pr_debug("%s: pattern reg is 0x%x", clk_hw_get_name(&common->hw), reg); diff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h index c1a7159b89c3..e94cef141c7d 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.h +++ b/drivers/clk/sunxi-ng/ccu_sdm.h @@ -33,21 +33,28 @@ struct ccu_sdm_internal { u32 table_size; /* early SoCs don't have the SDM enable bit in the PLL register */ u32 enable; - /* second enable bit in tuning register */ - u32 tuning_enable; - u16 tuning_reg; + /* second enable bit in pattern0 register */ + u32 pat0_enable; + u16 pat0_reg; + /* on some platforms, the sdm enable bit in pattern1 register */ + u32 pat1_enable; + u16 pat1_reg; }; -#define _SUNXI_CCU_SDM(_table, _enable, \ - _reg, _reg_enable) \ - { \ - .table = _table, \ - .table_size = ARRAY_SIZE(_table), \ - .enable = _enable, \ - .tuning_enable = _reg_enable, \ - .tuning_reg = _reg, \ +#define _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, _pat1, _pat1_enable) \ + { \ + .table = _table, \ + .table_size = ARRAY_SIZE(_table), \ + .enable = _enable, \ + .pat0_enable = _pat0_enable, \ + .pat0_reg = _pat0, \ + .pat1_enable = _pat1_enable, \ + .pat1_reg = _pat1, \ } +#define _SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable) \ + _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, 0, 0) + bool ccu_sdm_helper_is_enabled(struct ccu_common *common, struct ccu_sdm_internal *sdm); void ccu_sdm_helper_enable(struct ccu_common *common, -- 2.55.0