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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1790005190; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=yr+8wfepGJSzc2qtm1TGkRCYbSHT9qEg9LiJnRKrxQ8=; b=Ir7C6ObACWcK3Cpc6zHz7Bvzc1eOMP1AsSop+zNzBWZmgHdCRKcxm6MDSMXJDc7r EhU5UkKOvY57DhrBFSAa7em0lxabWE3l4/QWOrabHXPClEz5yBJ4OLYKMx7qaxQLJhb p7Nzj2yDnqsNDNFpQswuTCC+ueCtEHKj5b9XXnGw= Received: by smtp.zohomail.com with SMTPS id 1790005188789863.1154762542147; Mon, 21 Sep 2026 08:39:48 -0700 (PDT) From: Junhui Liu Date: Mon, 21 Sep 2026 23:38:03 +0800 Subject: [PATCH v4 5/8] clk: sunxi-ng: a733: Add bus clocks support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260921-a733-clk-v4-5-9c184ebe9ac1@pigmoral.tech> References: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> In-Reply-To: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5474; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=L+ba19ASGMNMcM0lopLuNo40rXkmo8NE8ZY6JBZMrd0=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLI2+ldWHFoXvTGv2PvdpNa/KZ9Wvit3yn5U+eDq6Uczo /YGTzrS1FHKwiDGxSArpsjC5S/+z1qH59sRgdb7MHNYmUCGMHBxCsBEjjAw/OEIs11bYaHozScX 18T1V4A9VaBLw9P73GKeJYs5Lx8vU2f4nxQtW2W0siHCwFO2TnTz7ln21+a+Fbao7rrxPvV78e2 X/AA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_084013_215288_F73C140B X-CRM114-Status: GOOD ( 14.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the essential bus clocks in the Allwinner A733 CCU, including AHB, APB0, APB1, APB_UART, and MBUS. These buses are necessary for many other functional modules. An additional trace clock is also added as it falls within the register address range of the bus clocks, even though it is not strictly a bus clock. The MBUS clock is marked as critical to ensure the memory bus remains operational at all times. And the hardware requires an update bit (bit 27) to be set so that the configuration takes effect and the updated parameters can be correctly read back for the MBUS clock. Tested-by: Jerome Brunet Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 90 ++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c index 430a535919c6..00c61806c29b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -18,6 +18,7 @@ #include "ccu_div.h" #include "ccu_gate.h" +#include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nkmp.h" #include "ccu_nm.h" @@ -68,6 +69,16 @@ static const struct clk_hw *pll_ref_hws[] = { &pll_ref_clk.common.hw }; +/* + * There is a non-software-configurable mux selecting between the DCXO and the + * PLL_REF in hardware, whose output is fed to the sys-24M clock. Although both + * sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor clock to + * provide logical separation: + * - pll-ref is dedicated to feeding other PLLs + * - sys-24M serves as reference clock for downstream functional modules + */ +static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); + #define SUN60I_A733_PLL_DDR_REG 0x020 static struct ccu_nkmp pll_ddr_clk = { .enable = BIT(27), @@ -414,6 +425,72 @@ static SUNXI_CCU_M_HWS_WITH_GATE(pll_de_3x_clk, "pll-de-3x", pll_de_hws, SUN60I_A733_PLL_DE_REG, 16, 3, BIT(26), 0); +/************************************************************************** + * bus clocks * + **************************************************************************/ + +static const struct clk_parent_data ahb_apb_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static const struct clk_parent_data apb_uart_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x538, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static const struct clk_parent_data trace_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name = "losc" }, + { .fw_name = "iosc" }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph0_400M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data mbus_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph1_600M_clk.hw }, + { .hw = &pll_ddr_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .hw = &pll_periph1_400M_clk.hw }, + { .hw = &pll_npu_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the common @@ -448,11 +525,18 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &pll_de_clk.common, &pll_de_4x_clk.common, &pll_de_3x_clk.common, + &ahb_clk.common, + &apb0_clk.common, + &apb1_clk.common, + &apb_uart_clk.common, + &trace_clk.common, + &mbus_clk.common, }; static struct clk_hw_onecell_data sun60i_a733_hw_clks = { .hws = { [CLK_PLL_REF] = &pll_ref_clk.common.hw, + [CLK_SYS_24M] = &sys_24M_clk.hw, [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw, [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw, @@ -494,6 +578,12 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_PLL_DE] = &pll_de_clk.common.hw, [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw, [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB_UART] = &apb_uart_clk.common.hw, + [CLK_TRACE] = &trace_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, }, .num = CLK_FANOUT3 + 1, }; -- 2.55.0