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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d4bb6be7b3sm60201b6e.0.2026.09.21.17.45.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 17:45:25 -0700 (PDT) From: James Hilliard Subject: [PATCH net-next v5 0/3] net: stmmac: add Allwinner H616 EMAC1 support Date: Mon, 21 Sep 2026 18:45:23 -0600 Message-Id: <20260921-submit-h616-emac1-v1-v5-0-ada661ed9e9b@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/43OwWrDMAwG4FcpPs/Fkh0n2WnvMXqwHKVxWZIRu 6Gj5N3npjuEskJBFyHp+3UVkafAUbzvrmLiOcQwDrkp3nbCd244sgxN7gUqtKoGI+OZ+pBkZ8F K7p0HOYMEo0ulK4OOSOTT74nbcFnZTzFwkgNfkjjcJ1k4sU839bbbhZjG6Wf9YIb14i+s+D8sl 5JQFw0rImgr93HsXfja+7FfI2Z8BcGMaETSyEYx1Y+I3iLlE0RnxKKnSoNlqOkRMRsE1RPEZKT SpmxaRqay2SLLsvwC4mFjqqMBAAA= X-Change-ID: 20260914-submit-h616-emac1-v1-143703842abb To: Richard Genoud , Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Coquelin , Alexandre Torgue , LABBE Corentin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Jose Abreu Cc: Alastair D'Silva , Maxime Ripard , James Hilliard , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Andre Przywara X-Mailer: b4 0.15.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_174528_000813_1C7204DF X-CRM114-Status: GOOD ( 18.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The H616 secondary EMAC supports RMII at 10/100 Mbps and uses a separate system-control clock register at offset 0x34. Add its binding and a sun8i stmmac variant using that register. A distinct compatible without an older fallback prevents the driver from using EMAC0's clock register. EMAC1 connects internally to the co-packaged AC200 or AC300 EPHY and has no external PHY pins. Leave PHY initialization to the PHY driver instead of using the H3 internal-PHY controls. The RMII-only variant does not expose the RGMII clock-delay properties. First move the MAC software reset from probe to the DMA reset callback, after PHY initialization. This lets the MAC and its MDIO bus remain registered when the PHY driver or one of its suppliers is not ready yet. Mask interrupts before requesting reset and clear DMA and interrupt state even if it times out. Keep the separate H3 MDIO-mux reset sequence unchanged. The AC200/AC300 EPHY driver and package bindings are already in net-next. This series separates the H616 EMAC1 MAC driver and binding support from the earlier combined series. PWM, MFD and device-tree enablement are being handled separately. Signed-off-by: James Hilliard --- Changes in v5: - Split the three generic phylink/stmmac recovery fixes into a separate net series, as requested by Maxime Chevallier. Keep the sun8i MAC-reset change, EMAC1 binding and variant in this net-next series. - Add the originating driver's Fixes tag to the sun8i reset patch. - Link to v4: https://patch.msgid.link/20260920-submit-h616-emac1-v1-v4-0-8347dfe2eb7d@gmail.com Changes in v4: - Add a prerequisite stmmac core fix closing the interface after a failed MTU-change reopen without repeating DMA, IRQ or NAPI teardown. - Close the interface after failed hardware resume, and let phylink finish shutdown directly from its suspended state. - Retain DMA and interrupt-register clearing when the sun8i MAC reset times out, and return the original reset error. - Link to v3: https://patch.msgid.link/20260917-submit-h616-emac1-v1-v3-0-62cb8316e19b@gmail.com Changes in v3: - Add a prerequisite fix moving the MAC software reset to the DMA reset callback, after PHY initialization, so delayed module loading and deferred PHY probes do not tear down the MAC and its MDIO bus. - Preserve the H3 MDIO-mux reset and propagate hardware-reset failures through the normal stmmac hardware-setup error path. - Add Alastair D'Silva to Cc and rebase onto current net-next. - Link to v2: https://patch.msgid.link/20260915-submit-h616-emac1-v1-v2-0-322b32e40eb9@gmail.com Changes in v2: - Drop EMAC1 TX/RX clock-delay property support and keep the existing RGMII-only delay descriptions unchanged, as requested by Maxime Ripard. - Clarify that EMAC1 connects internally to a co-packaged PHY, not an external PHY or the H3-style internal-PHY controls. - Rebase onto current net-next. - Link to v1: https://patch.msgid.link/20260915-submit-h616-emac1-v1-v1-0-195de0bb1f8a@gmail.com To: Maxime Chevallier To: Andrew Lunn To: "David S. Miller" To: Eric Dumazet To: Jakub Kicinski To: Paolo Abeni To: Chen-Yu Tsai To: Jernej Skrabec To: Samuel Holland To: Maxime Coquelin To: Alexandre Torgue To: LABBE Corentin To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Maxime Ripard To: Giuseppe Cavallaro To: Jose Abreu Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org --- James Hilliard (3): net: stmmac: sun8i: reset the MAC after PHY initialization dt-bindings: net: allwinner: add H616 EMAC1 net: stmmac: sun8i: add support for Allwinner H616 EMAC1 .../bindings/net/allwinner,sun8i-a83t-emac.yaml | 13 ++++ .../devicetree/bindings/net/snps,dwmac.yaml | 2 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 69 +++++++++++++--------- 3 files changed, 57 insertions(+), 27 deletions(-) --- base-commit: 1b4efa0399f549d9b9bf82b3e2450e10a06d65b8 change-id: 20260914-submit-h616-emac1-v1-143703842abb Best regards, -- James Hilliard