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Mon, 21 Sep 2026 11:26:50 -0700 (PDT) Received: from dev-ag.figment.co.za ([192.145.132.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4872446067asm25126184f8f.12.2026.09.21.11.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 11:26:49 -0700 (PDT) From: Andrew Gaylard To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, qinjian@cqplus1.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux@armlinux.org.uk, Andrew Gaylard Subject: [PATCH v3 5/6] arm: dts: sunplus: add Tibbo LTPP3G2 board Date: Mon, 21 Sep 2026 20:26:19 +0200 Message-ID: <20260921182620.17597-6-ag@ffroot.co.za> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260921182620.17597-1-ag@ffroot.co.za> References: <20260921182620.17597-1-ag@ffroot.co.za> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_112652_996222_B31ACF8E X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a DTS for the Tibbo LTPP3G2 board, which uses the Sunplus SP7021 SoC. The initial DTS was provided by Sunplus Technology Co. and has been adapted for upstream with permission. The board features eMMC, SPI, a bit-banged I2C EEPROM (Atmel 24C16), PWM output to a buzzer, a watchdog, RTC, and two GPIO LEDs (heartbeat and MMC activity). Signed-off-by: Andrew Gaylard --- MAINTAINERS | 6 + arch/arm/boot/dts/sunplus/Makefile | 5 +- .../dts/sunplus/sunplus-sp7021-ltpp3g2.dts | 183 ++++++++++++++++++ 3 files changed, 191 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts diff --git a/MAINTAINERS b/MAINTAINERS index 6e50747a621c..313107bea748 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3737,6 +3737,12 @@ F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sunplus,sp7021-clkc.h F: include/dt-bindings/reset/sunplus,sp7021-reset.h +ARM/TIBBO LTPP3G2 BOARD +M: Andrew Gaylard +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts + ARM/Synaptics SoC support M: Jisheng Zhang M: Sebastian Hesselbarth diff --git a/arch/arm/boot/dts/sunplus/Makefile b/arch/arm/boot/dts/sunplus/Makefile index 868f2ea0c127..25ba2e530c35 100644 --- a/arch/arm/boot/dts/sunplus/Makefile +++ b/arch/arm/boot/dts/sunplus/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_SP7021) += \ - sunplus-sp7021-demo-v3.dtb -dtb-$(CONFIG_SOC_SP7021) += \ - sunplus-sp7021-demo-v3.dtb + sunplus-sp7021-demo-v3.dtb \ + sunplus-sp7021-ltpp3g2.dtb diff --git a/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts new file mode 100644 index 000000000000..6e25ba07dd96 --- /dev/null +++ b/arch/arm/boot/dts/sunplus/sunplus-sp7021-ltpp3g2.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Tibbo LTPP board G2 + * + * Copyright (C) 2021 Sunplus Technology Co. + */ + +/dts-v1/; + +#include "sunplus-sp7021-achip.dtsi" + +/ { + compatible = "tibbo,ltpp3g2", "sunplus,sp7021"; + model = "Tibbo LTPP3G2"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MB */ + }; + + i2c_tps: i2c { + compatible = "i2c-gpio"; + sda-gpios = <&pctl 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pctl 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pins_i2ctps>; + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; + }; +}; + +&leds { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&gpio_leds_pins>; + pinctrl-1 = <&leds_s0_slp>; + led-0 { + label = "system-led"; + gpios = <&pctl 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + led-1 { + label = "SG"; + gpios = <&pctl 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pins_pwm>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart1>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart2>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart3>; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pins_btuart &pins_bt_reset>; + status = "disabled"; +}; + +&mmc0 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pctl { + pinctrl-names = "default"; + pinctrl-0 = <&pins_gpio_nobinded>; + + pins_pwm: pinmux-pwm-pins { + sunplus,pins = < + SPPCTL_IOPAD(48, SPPCTL_PCTL_G_PMUX, MUXF_PWM0, 0) + >; + }; + + pins_gpio_nobinded: pinmux-gpio-nobinded-pins { + sunplus,pins = < + SPPCTL_IOPAD(30, SPPCTL_PCTL_G_GPIO, 0, 0) /* was L2SW_LED_FLASH1 */ + SPPCTL_IOPAD(39, SPPCTL_PCTL_G_GPIO, 0, 0) /* was L2SW_LED_ON1 */ + >; + }; + + pins_i2ctps: pinmux-i2c-pins { + sunplus,pins = < + SPPCTL_IOPAD(1, SPPCTL_PCTL_G_GPIO, 0, + SPPCTL_PCTL_L_OU1 | SPPCTL_PCTL_L_ODR) + SPPCTL_IOPAD(2, SPPCTL_PCTL_G_GPIO, 0, + SPPCTL_PCTL_L_OU1 | SPPCTL_PCTL_L_ODR) + >; + }; + + gpio_leds_pins: pinmux-gpio-leds-pins { + sunplus,pins = < + SPPCTL_IOPAD(6, SPPCTL_PCTL_G_GPIO, 0, SPPCTL_PCTL_L_OUT) + SPPCTL_IOPAD(7, SPPCTL_PCTL_G_GPIO, 0, SPPCTL_PCTL_L_OUT) + >; + }; + + leds_s0_slp: pinmux-user-leds-s0-slp-pins { + sunplus,pins = < + SPPCTL_IOPAD(6, SPPCTL_PCTL_G_GPIO, 0, 0) + SPPCTL_IOPAD(7, SPPCTL_PCTL_G_GPIO, 0, 0) + >; + }; + + pins_uart1: pinmux-uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(8, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(9, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) + SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) + >; + }; + + pins_uart2: pinmux-uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(12, SPPCTL_PCTL_G_PMUX, MUXF_UA2_TX, 0) + SPPCTL_IOPAD(13, SPPCTL_PCTL_G_PMUX, MUXF_UA2_RX, 0) + SPPCTL_IOPAD(14, SPPCTL_PCTL_G_PMUX, MUXF_UA2_RTS, 0) + SPPCTL_IOPAD(15, SPPCTL_PCTL_G_PMUX, MUXF_UA2_CTS, 0) + >; + }; + + pins_uart3: pinmux-uart3-pins { + sunplus,pins = < + SPPCTL_IOPAD(16, SPPCTL_PCTL_G_PMUX, MUXF_UA3_TX, 0) + SPPCTL_IOPAD(17, SPPCTL_PCTL_G_PMUX, MUXF_UA3_RX, 0) + SPPCTL_IOPAD(18, SPPCTL_PCTL_G_PMUX, MUXF_UA3_RTS, 0) + SPPCTL_IOPAD(19, SPPCTL_PCTL_G_PMUX, MUXF_UA3_CTS, 0) + >; + }; + + /* AP6256 Bluetooth */ + pins_btuart: pinmux-btuart-pins { + sunplus,pins = < + SPPCTL_IOPAD(40, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RX, 0) + SPPCTL_IOPAD(41, SPPCTL_PCTL_G_PMUX, MUXF_UA4_TX, 0) + SPPCTL_IOPAD(56, SPPCTL_PCTL_G_PMUX, MUXF_UA4_RTS, 0) + SPPCTL_IOPAD(49, SPPCTL_PCTL_G_PMUX, MUXF_UA4_CTS, 0) + >; + }; + + pins_bt_reset: pinmux-bt-reset-pins { + sunplus,pins = < SPPCTL_IOPAD(82, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + +}; -- 2.53.0