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Tue, 22 Sep 2026 06:13:27 -0700 (PDT) Date: Tue, 22 Sep 2026 13:12:53 +0000 In-Reply-To: <20260922131259.2975334-1-smostafa@google.com> Mime-Version: 1.0 References: <20260922131259.2975334-1-smostafa@google.com> X-Mailer: git-send-email 2.55.0.1082.g2b9226bbc0-goog Message-ID: <20260922131259.2975334-21-smostafa@google.com> Subject: [PATCH v8 20/25] iommu/arm-smmu-v3-kvm: Emulate GBPA From: Mostafa Saleh To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com, Mostafa Saleh Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260922_141330_040154_6045C978 X-CRM114-Status: GOOD ( 16.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The last bit of emulation is GBPA. it must be always set to ABORT, as when the SMMU is disabled it's not allowed for the host to bypass the SMMU. That's is done by setting the GBPA to ABORT at init time, and host writes are always ignored and host reads always return ABORT. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index 00528380774f..6e023e968ed3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -215,6 +215,22 @@ static int smmu_send_cmd(struct hyp_arm_smmu_v3_device *smmu, return smmu_sync_cmd(smmu); } +static int smmu_abort_gbpa(struct hyp_arm_smmu_v3_device *smmu) +{ + int ret; + u32 reg; + + ret = smmu_wait(false, + (readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_UPDATE) == 0); + if (ret) + return ret; + + reg = readl_relaxed(smmu->base + ARM_SMMU_GBPA); + writel_relaxed(GBPA_UPDATE | GBPA_ABORT | reg, smmu->base + ARM_SMMU_GBPA); + return smmu_wait(false, + (readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_UPDATE) == 0); +} + /* Put the device in a state that can be probed by the host driver. */ static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu) { @@ -453,6 +469,10 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu) if (ret) goto out_ret; + ret = smmu_abort_gbpa(smmu); + if (ret) + goto out_ret; + return 0; out_ret: @@ -778,10 +798,16 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, val = smmu->host_ste_cfg; goto out_update_regs; } - /* Passthrough the register access for bisectability, handled later */ case ARM_SMMU_GBPA: - mask = read_write; - break; + if (len != sizeof(u32)) + break; + + /* Ignore write, always read to abort. */ + if (!is_write) { + val = GBPA_ABORT; + goto out_update_regs; + } + goto out_ret; case ARM_SMMU_CR0: if (len != sizeof(u32)) break; -- 2.55.0.1082.g2b9226bbc0-goog