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Wed, 23 Sep 2026 01:13:21 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Wed, 23 Sep 2026 16:13:18 +0800 Received: from gcnsap21.gcn.mediatek.inc (10.17.81.22) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Wed, 23 Sep 2026 16:13:06 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v10 04/10] media: mediatek: vcodec: Refactor Decoder profile & level Handling Date: Wed, 23 Sep 2026 16:12:40 +0800 Message-ID: <20260923081246.268182-5-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260923081246.268182-1-kyrie.wu@mediatek.com> References: <20260923081246.268182-1-kyrie.wu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260923_091328_295919_4CD18917 X-CRM114-Status: GOOD ( 15.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This commit refactors the handling of decoder parameters for H264, H265, and VP9 codecs by introducing a new structure to standardize supported level and profile information. By leveraging this change, chipset-specific conditional logic in the codec configuration functions is significantly reduced. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 16 ++ .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 12 ++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 165 ++++++++++-------- 3 files changed, 118 insertions(+), 75 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index d7ed7bfe7d50..bbfa6954d616 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -78,6 +78,16 @@ struct vdec_pic_info { unsigned int reserved; }; +/** + * struct mtk_vcodec_dec_params - decoder supported parameters + * @level: decoder supported vcodec level + * @profile: decoder supported vcodec profile + */ +struct mtk_vcodec_dec_params { + s64 level; + s64 profile; +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -100,6 +110,9 @@ struct vdec_pic_info { * @fw_type: firmware type (VPU, SCP, or VCP) * @fw_init: firmware-specific initialization callback * @chip_model: platforms configuration values + * @h264_params: H264 decoder default supported params + * @h265_params: H265 decoder default supported params + * @vp9_params: VP9 decoder default supported params */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -125,6 +138,9 @@ struct mtk_vcodec_dec_pdata { struct mtk_vcodec_fw *(*fw_init)(void *priv, enum mtk_vcodec_fw_use fw_use); unsigned int chip_model; + struct mtk_vcodec_dec_params h264_params; + struct mtk_vcodec_dec_params h265_params; + struct mtk_vcodec_dec_params vp9_params; }; /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c index e7ae90e8238e..bf3569e6b559 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c @@ -621,4 +621,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = { .fw_type = VPU, .fw_init = mtk_vcodec_fw_vpu_init, .chip_model = 8173, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_4_1, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index 2a03395ab30b..cbea445e5c2b 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -571,106 +571,49 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8192: - case 8188: - cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2; - break; - case 8195: - case 8196: - cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0; - break; - case 8183: - case 8186: - cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2; - break; - default: - cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1; - break; - } + struct mtk_vcodec_dec_dev *pdev = ctx->dev; + + cfg->max = pdev->vdec_pdata->h264_params.level; } static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; - break; - default: - cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; - break; - } + struct mtk_vcodec_dec_dev *pdev = ctx->dev; + + cfg->max = pdev->vdec_pdata->h264_params.profile; } static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; - break; - default: - cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; - break; - } + struct mtk_vcodec_dec_dev *pdev = ctx->dev; + + cfg->max = pdev->vdec_pdata->h265_params.level; } static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; - break; - default: - cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE; - break; - } + struct mtk_vcodec_dec_dev *pdev = ctx->dev; + + cfg->max = pdev->vdec_pdata->h265_params.profile; } static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8192: - case 8188: - cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; - break; - case 8186: - cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; - break; - default: - cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0; - break; - } + struct mtk_vcodec_dec_dev *pdev = ctx->dev; + + cfg->max = pdev->vdec_pdata->vp9_params.level; } static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_model) { - case 8188: - case 8195: - case 8196: - cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2; - break; - default: - cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_1; - break; - } + struct mtk_vcodec_dec_dev *pdev = ctx->dev; + + cfg->max = pdev->vdec_pdata->vp9_params.profile; } static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, @@ -938,6 +881,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = { .fw_type = SCP, .fw_init = mtk_vcodec_fw_scp_init, .chip_model = 8183, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; /* This platform data is used for one lat and one core architecture. */ @@ -979,6 +934,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = { .fw_type = SCP, .fw_init = mtk_vcodec_fw_scp_init, .chip_model = 8188, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = { @@ -987,6 +954,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = { .fw_type = SCP, .fw_init = mtk_vcodec_fw_scp_init, .chip_model = 8192, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_5_2, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = { @@ -995,6 +974,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = { .fw_type = SCP, .fw_init = mtk_vcodec_fw_scp_init, .chip_model = 8195, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = { @@ -1003,6 +994,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = { .fw_type = VCP, .fw_init = mtk_vcodec_fw_vcp_init, .chip_model = 8196, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2, + }, }; const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = { @@ -1028,4 +1031,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = { .fw_type = SCP, .fw_init = mtk_vcodec_fw_scp_init, .chip_model = 8186, + .h264_params = { + .level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + }, + .h265_params = { + .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + }, + .vp9_params = { + .level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1, + }, }; -- 2.51.0.windows.2