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Add an overlay supporting two such boards, each connected to one of the two CSI RX inputs on J722S-EVM. [1] https://www.arducam.com/downloads/datasheet/Arducam_V3Link_Datasheet.pdf Reviewed-by: Rishikesh Donadkar Signed-off-by: Vaishnav Achath Signed-off-by: Yemike Abhilash Chandra --- Changes in v3: - Rename fixed-clock node to the generic clock- form (Krzysztof) - Also rename fixed-clock label to lowercase - Override CSI2RX ports using &csiN_port0 labels instead of the full &cdns_csi2rxN node path, and drop duplicated properties (Krzysztof) - Fix minor DTS coding style issues (Sashiko) - Use GPL-2.0-only OR MIT license for consistency - Update copyright year to 2026 (Udit) arch/arm64/boot/dts/ti/Makefile | 4 + .../dts/ti/k3-j722s-evm-v3link-fusion.dtso | 197 ++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 3d503811168b..beb44ebe5277 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -212,6 +212,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo # Boards with J784s4 SoC k3-am69-aquila-clover-panel-cap-touch-10inch-dsi-dtbs := \ @@ -439,6 +440,8 @@ k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo k3-j722s-evm-fpdlink-fusion-dtbs := k3-j722s-evm.dtb \ k3-j722s-evm-fpdlink-fusion.dtbo +k3-j722s-evm-v3link-fusion-dtbs := k3-j722s-evm.dtb \ + k3-j722s-evm-v3link-fusion.dtbo k3-j742s2-evm-fpdlink-fusion-dtbs := k3-j742s2-evm.dtb \ k3-j721s2-evm-fusion.dtbo k3-j742s2-evm-usb0-type-a-dtbs := k3-j742s2-evm.dtb \ @@ -544,6 +547,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j722s-evm-fpdlink-fusion.dtb \ + k3-j722s-evm-v3link-fusion.dtb \ k3-j742s2-evm-fpdlink-fusion.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ k3-j784s4-evm-fpdlink-fusion.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso b/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso new file mode 100644 index 000000000000..a384168a460e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm-v3link-fusion.dtso @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for Arducam V3Link UC-A09 board + * https://www.arducam.com/fpd-link-3-cameras/ + * + * Copyright (C) 2026 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + clk_fusion_25mhz: clock-25000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&csi01_mux { + idle-state = <1>; +}; + +&csi23_mux { + idle-state = <1>; +}; + +&pca9543_0 { + #address-cells = <1>; + #size-cells = <0>; + + /* CAM0 I2C */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25mhz>; + + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + status = "disabled"; + }; + + port@1 { + reg = <1>; + status = "disabled"; + }; + + port@2 { + reg = <2>; + status = "disabled"; + }; + + port@3 { + reg = <3>; + status = "disabled"; + }; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + + port@5 { + reg = <5>; + status = "disabled"; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + /* CAM1 I2C */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + deser@30 { + compatible = "ti,ds90ub960-q1"; + reg = <0x30>; + + clock-names = "refclk"; + clocks = <&clk_fusion_25mhz>; + + i2c-alias-pool = <0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; + + deserializer_1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + status = "disabled"; + }; + + port@1 { + reg = <1>; + status = "disabled"; + }; + + port@2 { + reg = <2>; + status = "disabled"; + }; + + port@3 { + reg = <3>; + status = "disabled"; + }; + + /* CSI-2 TX */ + port@4 { + reg = <4>; + ds90ub960_1_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy1>; + }; + }; + + port@5 { + reg = <5>; + status = "disabled"; + }; + }; + + deserializer_1_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi2_phy1: endpoint { + remote-endpoint = <&ds90ub960_1_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; -- 2.34.1