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Link: https://www.ti.com/tool/DS90UB954-Q1EVM Reviewed-by: Rishikesh Donadkar Signed-off-by: Yemike Abhilash Chandra --- Changes in v3: - Rename fixed-clock node to the generic clock- form (Krzysztof) - Also rename fixed-clock label to lowercase - Override CSI2RX port using &csi0_port0 label instead of the full &cdns_csi2rx0 node path, and drop duplicated properties (Krzysztof) - Update copyright year to 2026 (Udit) arch/arm64/boot/dts/ti/Makefile | 4 + .../arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso | 83 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index a66d11359bd4..9d3ab69267a6 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -177,6 +177,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-ub954.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-fpdlink-fusion.dtbo @@ -425,6 +426,8 @@ k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie1-ep.dtbo +k3-j721e-evm-ub954-dtbs := k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-ub954.dtbo k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721e-sk-fpdlink-fusion-dtbs := k3-j721e-sk.dtb \ @@ -551,6 +554,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-fpdlink-fusion.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-evm-pcie1-ep.dtb \ + k3-j721e-evm-ub954.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721e-sk-fpdlink-fusion.dtb \ k3-j721e-sk-v3link-fusion.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso new file mode 100644 index 000000000000..8db95c977071 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-ub954.dtso @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DT Overlay for DS90UB954-Q1EVM FPDLink-III deserializer board on J721E EVM + * https://www.ti.com/tool/DS90UB954-Q1EVM + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + clk_fusion_25mhz: clock-25000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&main_i2c6 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + deser@3d { + compatible = "ti,ds90ub954-q1"; + reg = <0x3d>; + clock-names = "refclk"; + clocks = <&clk_fusion_25mhz>; + i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>; + + deserializer_0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + status = "disabled"; + }; + + port@1 { + reg = <1>; + status = "disabled"; + }; + + /* CSI-2 TX */ + port@2 { + reg = <2>; + ds90ub960_0_csi_out: endpoint { + data-lanes = <1 2 3 4>; + clock-lanes = <0>; + link-frequencies = /bits/ 64 <800000000>; + remote-endpoint = <&csi2_phy0>; + }; + }; + }; + + deserializer_0_links: links { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2_phy0: endpoint { + remote-endpoint = <&ds90ub960_0_csi_out>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <800000000>; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; -- 2.34.1