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Wed, 23 Sep 2026 11:39:14 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df6a5dc32csm15528625ad.53.2026.09.23.11.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 11:39:14 -0700 (PDT) From: Rosen Penev To: devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ray Jui , Scott Branden , Broadcom internal kernel review list , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM IPROC ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] ARM: dts: alamo: use qca8337 internal PHYs Date: Wed, 23 Sep 2026 11:39:12 -0700 Message-ID: <20260923183912.13389-1-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260923_113916_602041_E2F218D7 X-CRM114-Status: GOOD ( 11.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The QCA8337 switch has a managed internal MDIO bus for its built-in PHYs. Move the PHY nodes from the external mdio@0 bus into a subnode of the switch, and mark the connected switch ports with phy-mode = "internal", so the ports are linked to the correct PHYs. Assisted-by: LLM Signed-off-by: Rosen Penev --- .../dts/broadcom/bcm958625-meraki-alamo.dtsi | 100 +++++++++++------- 1 file changed, 60 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi index c54451dde6dd..d0199c07707c 100644 --- a/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm958625-meraki-alamo.dtsi @@ -85,26 +85,6 @@ mdio@0 { #address-cells = <1>; #size-cells = <0>; - phy_port6: phy@0 { - reg = <0>; - }; - - phy_port7: phy@1 { - reg = <1>; - }; - - phy_port8: phy@2 { - reg = <2>; - }; - - phy_port9: phy@3 { - reg = <3>; - }; - - phy_port10: phy@4 { - reg = <4>; - }; - switch@10 { compatible = "qca,qca8337"; reg = <0x10>; @@ -128,60 +108,70 @@ fixed-link { port@1 { reg = <1>; label = "lan8"; + phy-mode = "internal"; phy-handle = <&phy_port6>; }; port@2 { reg = <2>; label = "lan9"; + phy-mode = "internal"; phy-handle = <&phy_port7>; }; port@3 { reg = <3>; label = "lan10"; + phy-mode = "internal"; phy-handle = <&phy_port8>; }; port@4 { reg = <4>; label = "lan11"; + phy-mode = "internal"; phy-handle = <&phy_port9>; }; port@5 { reg = <5>; label = "lan12"; + phy-mode = "internal"; phy-handle = <&phy_port10>; }; }; - }; - }; - mdio-mii@2000 { - reg = <0x2000>; - #address-cells = <1>; - #size-cells = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; - phy_port1: phy@0 { - reg = <0>; - }; + phy_port6: ethernet-phy@0 { + reg = <0>; + }; - phy_port2: phy@1 { - reg = <1>; - }; + phy_port7: ethernet-phy@1 { + reg = <1>; + }; - phy_port3: phy@2 { - reg = <2>; - }; + phy_port8: ethernet-phy@2 { + reg = <2>; + }; - phy_port4: phy@3 { - reg = <3>; - }; + phy_port9: ethernet-phy@3 { + reg = <3>; + }; - phy_port5: phy@4 { - reg = <4>; + phy_port10: ethernet-phy@4 { + reg = <4>; + }; + }; }; + }; + + mdio-mii@2000 { + reg = <0x2000>; + #address-cells = <1>; + #size-cells = <0>; switch@10 { compatible = "qca,qca8337"; @@ -206,33 +196,63 @@ fixed-link { port@1 { reg = <1>; label = "lan3"; + phy-mode = "internal"; phy-handle = <&phy_port1>; }; port@2 { reg = <2>; label = "lan4"; + phy-mode = "internal"; phy-handle = <&phy_port2>; }; port@3 { reg = <3>; label = "lan5"; + phy-mode = "internal"; phy-handle = <&phy_port3>; }; port@4 { reg = <4>; label = "lan6"; + phy-mode = "internal"; phy-handle = <&phy_port4>; }; port@5 { reg = <5>; label = "lan7"; + phy-mode = "internal"; phy-handle = <&phy_port5>; }; }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: ethernet-phy@0 { + reg = <0>; + }; + + phy_port2: ethernet-phy@1 { + reg = <1>; + }; + + phy_port3: ethernet-phy@2 { + reg = <2>; + }; + + phy_port4: ethernet-phy@3 { + reg = <3>; + }; + + phy_port5: ethernet-phy@4 { + reg = <4>; + }; + }; }; }; }; -- 2.55.0