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Thu, 24 Sep 2026 15:53:42 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-34141d2fe4bsm1631877eec.4.2026.09.24.15.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 15:53:41 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1x9sJw-00000000efs-2Wk8; Thu, 24 Sep 2026 19:53:40 -0300 Date: Thu, 24 Sep 2026 19:53:40 -0300 From: Jason Gunthorpe To: Daniel Mentz Cc: Vijayanand Jitta , Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Prakash Gupta Subject: Re: [PATCH v5] iommu/io-pgtable-arm: Add support for contiguous hint bit Message-ID: <20260924225340.GC16465@ziepe.ca> References: <20260921-iommu_contig_hint-v5-1-e7fbd1c3774d@oss.qualcomm.com> <20260924001502.GO1540250@ziepe.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260924_155343_135901_701241B2 X-CRM114-Status: GOOD ( 26.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 24, 2026 at 11:49:50AM -0700, Daniel Mentz wrote: > On Wed, Sep 23, 2026 at 5:15 PM Jason Gunthorpe wrote: > > > > On Mon, Sep 21, 2026 at 04:44:07PM +0530, Vijayanand Jitta wrote: > > > From: Prakash Gupta > > > > > > Add support for the contiguous hint (CONT) bit in ARM LPAE page tables. > > > When a set of consecutive PTEs map a naturally aligned contiguous block of > > > memory, set CONT on every descriptor in that group so the hardware can > > > combine translations and improve TLB reach. > > > > > > Advertise the supported CONT group sizes in pgsize_bitmap. Callers select > > > those sizes through the normal page-size selection path; io-pgtable-arm > > > then installs the corresponding tagged descriptors directly. A partial > > > unmap of a tagged CONT group is rejected before modifying any descriptor, > > > so a rejected request cannot leave the group partly unmapped. > > > > > > The IO_PGTABLE_QUIRK_ARM_NO_CONT_HINT quirk allows SMMU drivers to disable > > > CONT support for hardware with implementation-specific errata. > > > > smmuv3 has this errata, it must be disabled there too. I didn't notice > > it in this patch? > > SMMU is an architecture specification. I am not aware of errors in > this architecture specification that would preclude the usage of the > contiguous bit. I understand that Arm MMU-700 has the following > erratum > > 3777127 Under invalidation in TBU possible when using contiguous page > table entries And a neoverse one too. > The recommended workaround is described as > > "Ensure that contiguous page tables are removed using a single range > invalidation. Arm recommends using range invalidations to remove > contiguous entries anyway for performance reasons." > > and I believe we are already doing this. No we aren't. Go read my fix on this: https://lore.kernel.org/linux-iommu/1-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com/ I have another patch that fixes it for iommu domain mappings too. Jason