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Thu, 24 Sep 2026 16:06:04 -0700 (PDT) Received: from ziepe.ca ([130.41.10.202]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3414407d18fsm1480231eec.10.2026.09.24.16.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 16:06:03 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1x9sVu-00000000fXu-3DDy; Thu, 24 Sep 2026 20:06:02 -0300 Date: Thu, 24 Sep 2026 20:06:02 -0300 From: Jason Gunthorpe To: Peter Griffin Cc: Will Deacon , Robin Murphy , "Joerg Roedel (AMD)" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pranjal Shrivastava , Daniel Mentz , Mostafa Saleh , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, jyescas@google.com Subject: Re: [PATCH v2 2/2] iommu/arm-smmu-v3: Add support for arm,instdata-override DT property Message-ID: <20260924230602.GE16465@ziepe.ca> References: <20260911-arm-smmu-v3-instcfg-override-v2-0-5804e4f400b5@linaro.org> <20260911-arm-smmu-v3-instcfg-override-v2-2-5804e4f400b5@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260911-arm-smmu-v3-instcfg-override-v2-2-5804e4f400b5@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260924_160605_679287_D3FC2426 X-CRM114-Status: GOOD ( 19.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 11, 2026 at 09:21:06PM +0000, Peter Griffin wrote: > The Google Tensor G5 SoC (Laguna) has a silicon errata with the SMMU > integration where the AxPROT[2] signal is always 1, which makes all > transactions appear as instructions. > > To avoid F_PERMISSION faults (due to the VMSAv8-64 requirement that > unprivilieged writable buffers are treated as Privileged Execute-Never > (PXN)), as a software workaround we make use of the INSTCFG override > feature to force all incoming traffic to data. > > To enable this workaround, the "arm,instdata-override" DT property can be > provided in the device tree entry for the SMMU, similar to how existing > errata workarounds are handled by this driver. > > Note this is added for "stage-1" and "stage-2" but we intentionally leave > out "bypass" as nothing is downstream of the SMMU that makes use of the > Instruction/Data attribute. > > Signed-off-by: Pranjal Shrivastava > [peter.griffin: ported to upstream, updated commit message, remove > feature flag] > Signed-off-by: Peter Griffin > --- > Changes in v2 > - Fixup incorrect bracket (Sashiko / Nicolin) > - Add more verbose description of the issue (Will/Robin) > - Add note about why "bypass" is not required (Nicolin) > - Remove ARM_SMMU_FEAT_PERMS_OVR flag (Nicolin) > - Move check closer to IDR1_ATTR_TYPES_OVR read > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 +++++++++++++++++++++---- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++++++ > 2 files changed, 27 insertions(+), 4 deletions(-) Reviewed-by: Jason Gunthorpe Jason