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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a0976cacbesm8151528a91.13.2026.09.24.21.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 21:49:31 -0700 (PDT) From: phucduc.bui@gmail.com To: Mark Brown , AngeloGioacchino Del Regno , Trevor Wu Cc: Liam Girdwood , Matthias Brugger , Jaroslav Kysela , Takashi Iwai , Kuninori Morimoto , cassiogabrielcontato@gmail.com, Mukesh Ojha , Liviu Dudau , Haotian Zhang , HariKrishna Sagala , linux-sound@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH 01/14] ASoC: mediatek: mt8195: Fix tuner clock error handling Date: Fri, 25 Sep 2026 11:48:55 +0700 Message-ID: <20260925044908.450775-2-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260925044908.450775-1-phucduc.bui@gmail.com> References: <20260925044908.450775-1-phucduc.bui@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260924_214932_256739_259ED0B1 X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: bui duc phuc Check and propagate errors from mt8195_afe_enable_clk(). If enabling the tuner clock fails, disable the previously enabled APLL clock. Fixes: ff5a90173d98 ("ASoC: mediatek: mt8195: enable apll tuner") Signed-off-by: bui duc phuc --- sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 24 +++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c index 618d8400913a..ec1ea5b988ff 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c @@ -241,21 +241,35 @@ static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe, unsigned int id) { struct mt8195_afe_private *afe_priv = afe->platform_priv; + int ret; switch (id) { case MT8195_AUD_PLL1: - mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); - mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); + ret = mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); + if (ret) + return ret; + ret = mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); + if (ret) { + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); + return ret; + } break; case MT8195_AUD_PLL2: - mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); - mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); + ret = mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); + if (ret) + return ret; + ret = mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); + if (ret) { + mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); + return ret; + } break; default: + ret = 0; break; } - return 0; + return ret; } static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe, -- 2.43.0