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Thu, 24 Sep 2026 22:21:38 -0700 (PDT) Received: from AHERLNXVDANI01.lgs-net.com ([193.8.40.126]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4887a6450a3sm3699394f8f.25.2026.09.24.22.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 22:21:37 -0700 (PDT) From: =?UTF-8?q?Daniel=20Via=C3=B1o?= To: Alexandre Belloni Cc: Michal Simek , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Daniel=20Via=C3=B1o?= , stable@vger.kernel.org Subject: [PATCH v2] rtc: zynqmp: Enable crystal oscillator when setting time Date: Fri, 25 Sep 2026 07:20:15 +0200 Message-ID: <20260925052015.22019-1-danividanivi@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260924_222140_572536_EF6B46F9 X-CRM114-Status: GOOD ( 18.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The RTC_OSC_EN macro was defined when the driver was originally introduced, but was never asserted by the driver. On cold boots, after battery exhaustion, or on platforms where firmware does not configure RTC_CTRL, the oscillator remains disabled and the counter never ticks. Unconditionally enabling the oscillator during driver initialization would cause the RTC to free-run from an uninitialized or stale counter value, reporting an untrusted time to userspace. Instead, keep the oscillator disabled until a valid time is programmed: guard xlnx_rtc_read_time() on RTC_OSC_EN and return -EINVAL when it is not set, and assert RTC_OSC_EN in xlnx_rtc_set_time() once valid time is programmed so the RTC can free-run. Per the Zynq UltraScale+ TRM (UG1085), bit 24 (OSC_CNTRL) is a static level enable for the crystal inverter rather than an edge-triggered reset; asserting it from set_time() is non-destructive and will not glitch an already-running oscillator. Tested on Zynq UltraScale+ hardware, confirming that read_time returns -EINVAL while the oscillator is disabled, and advances reliably after setting time. Fixes: 11143c19eb57 ("rtc: add xilinx zynqmp rtc driver") Cc: stable@vger.kernel.org Signed-off-by: Daniel Viaño --- v2: - Leave xlnx_init_rtc() unchanged so the oscillator is not enabled on probe - Return -EINVAL in xlnx_rtc_read_time() when RTC_OSC_EN is not set - Enable RTC_OSC_EN in xlnx_rtc_set_time() once valid time is programmed drivers/rtc/rtc-zynqmp.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c index 5bcb7536e973..6c3ba8f1aa57 100644 --- a/drivers/rtc/rtc-zynqmp.c +++ b/drivers/rtc/rtc-zynqmp.c @@ -59,6 +59,8 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); unsigned long new_time; + u32 rtc_ctrl; + /* * The value written will be updated after 1 sec into the * seconds read register, so we need to program time +1 sec @@ -78,6 +80,14 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) */ writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); + /* + * Now that the time is valid, start the crystal oscillator so the + * RTC free-runs. + */ + rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); + rtc_ctrl |= RTC_OSC_EN; + writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); + return 0; } @@ -87,6 +97,9 @@ static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm) unsigned long read_time; struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); + if (!(readl(xrtcdev->reg_base + RTC_CTRL) & RTC_OSC_EN)) + return -EINVAL; + status = readl(xrtcdev->reg_base + RTC_INT_STS); if (status & RTC_INT_SEC) { -- 2.53.0