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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-494877590e5sm4489452fac.13.2026.09.27.11.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Sep 2026 11:52:29 -0700 (PDT) From: James Hilliard Date: Sun, 27 Sep 2026 12:52:19 -0600 Subject: [PATCH net-next v6 1/3] net: stmmac: sun8i: reset the MAC after PHY initialization MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260927-submit-h616-emac1-v1-v6-1-e64971f4e414@gmail.com> References: <20260927-submit-h616-emac1-v1-v6-0-e64971f4e414@gmail.com> In-Reply-To: <20260927-submit-h616-emac1-v1-v6-0-e64971f4e414@gmail.com> To: Richard Genoud , Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Coquelin , Alexandre Torgue , LABBE Corentin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Jose Abreu Cc: Alastair D'Silva , Maxime Ripard , James Hilliard , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260927_115233_193373_F6C5C193 X-CRM114-Status: GOOD ( 22.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MAC software reset needs a running receive clock from the PHY. Resetting the MAC at the end of probe therefore fails when the PHY driver has not been loaded or its probe has deferred on a missing supplier. The failure removes the MAC and its MDIO bus, so loading the missing driver later cannot recover the interface without reprobing the MAC. Perform the software reset in the DMA reset callback instead. The stmmac core calls it during hardware setup after attaching and initializing the PHY, and resumes a suspended PHY before reopening or resuming the MAC. Mask interrupts before requesting the reset and retain the existing DMA and interrupt-register clearing even if the reset times out. Return reset errors through the normal hardware-setup error path. Remove the unconditional reset from probe. Keep the separate H3 MDIO-mux reset after switching the mux and powering the selected PHY, since it is needed to latch the selected interface before MDIO accesses. Fixes: 9f93ac8d4085 ("net-next: stmmac: Add dwmac-sun8i") Tested-by: Maxime Chevallier Reviewed-by: Maxime Chevallier Signed-off-by: James Hilliard --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 53 +++++++++++------------ 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 38d7e71de925..5691da796454 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -269,11 +269,33 @@ static const struct emac_variant emac_variant_h6 = { #define SYSCON_ETCS_EXT_GMII 0x1 #define SYSCON_ETCS_INT_GMII 0x2 +static int sun8i_dwmac_reset(void __iomem *ioaddr) +{ + u32 v; + + v = readl(ioaddr + EMAC_BASIC_CTL1); + writel(v | 0x01, ioaddr + EMAC_BASIC_CTL1); + + /* The timeout was previously set to 10ms, but some board (OrangePI0) + * need more if no cable plugged. 100ms seems OK + */ + return readl_poll_timeout(ioaddr + EMAC_BASIC_CTL1, v, + !(v & 0x01), 100, 100000); +} + /* sun8i_dwmac_dma_reset() - reset the EMAC * Called from stmmac via stmmac_dma_ops->reset */ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) { + int ret; + + writel(0, ioaddr + EMAC_INT_EN); + + /* The PHY receive clock must be running for the reset to complete. */ + ret = sun8i_dwmac_reset(ioaddr); + + /* Leave DMA and interrupts disabled even if the reset timed out. */ writel(0, ioaddr + EMAC_RX_CTL1); writel(0, ioaddr + EMAC_TX_CTL1); writel(0, ioaddr + EMAC_RX_FRM_FLT); @@ -281,7 +303,7 @@ static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) writel(0, ioaddr + EMAC_TX_DESC_LIST); writel(0, ioaddr + EMAC_INT_EN); writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); - return 0; + return ret; } /* sun8i_dwmac_dma_init() - initialize the EMAC @@ -738,27 +760,6 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, writel(v, ioaddr + EMAC_TX_FLOW_CTL); } -static int sun8i_dwmac_reset(struct stmmac_priv *priv) -{ - u32 v; - int err; - - v = readl(priv->ioaddr + EMAC_BASIC_CTL1); - writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); - - /* The timeout was previously set to 10ms, but some board (OrangePI0) - * need more if no cable plugged. 100ms seems OK - */ - err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, - !(v & 0x01), 100, 100000); - - if (err) { - dev_err(priv->device, "EMAC reset timeout\n"); - return err; - } - return 0; -} - /* Search in mdio-mux node for internal PHY node and get its clk/reset */ static int get_ephy_nodes(struct stmmac_priv *priv) { @@ -899,7 +900,9 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, /* After changing syscon value, the MAC need reset or it will * use the last value (and so the last PHY set). */ - ret = sun8i_dwmac_reset(priv); + ret = sun8i_dwmac_reset(priv->ioaddr); + if (ret) + dev_err(priv->device, "EMAC reset timeout\n"); } return ret; } @@ -1221,10 +1224,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Failed to register mux\n"); goto dwmac_mux; } - } else { - ret = sun8i_dwmac_reset(priv); - if (ret) - goto dwmac_remove; } pm_runtime_put(&pdev->dev); -- 2.53.0