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Mon, 28 Sep 2026 04:33:10 -0500 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 28 Sep 2026 04:33:09 -0500 Received: from xhdtunimkar40.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 04:33:06 -0500 From: Tushar Nimkar Subject: [PATCH v4 0/2] Add Xilinx Versal NET SMMU CSR interrupt controller support Date: Mon, 28 Sep 2026 15:03:02 +0530 Message-ID: <20260928-smmu-changes-v2-v4-0-3c79a14cd806@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAE40umoC/2WN3QqDIBiGbyU8nsO0THe0+xg78K/lwAot2Yjuf VqMDYLv5OV9n+dbQDDemgAuxQK8iTbYoU+hOhVAdaJ/GGh1ygAjTBEvGxicm+FeBRgx5KptKlJ ryikHiRq9ae1rM97uew6zfBo1ZU1edDZMg39vLyPOu6+dHezpEBRaC8pKITkjV+H0WQ0OZHckf zQmR5okmjVSIy4Fp6j+0eu6fgDLrB8z/AAAAA== X-Change-ID: 20260917-smmu-changes-v2-9cf7435d6969 To: Anirudha Sarangi , Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek CC: , , , , Tushar Nimkar , Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ihCC49/ONdTiBm3sEWOV2XoWZLQuYsZ16EczrB9PFZ5QDxnU87dNsZoQcKIASV+IwmHpM0VlCT/uslCOpaoAvbpaRqTnlGN4v2fWPeRNlqFGnuRGNRqX86eSlLCQCFNr0KuVHGMIUuqbG6bKHyJFL1exWmYKbPbtaP0x9CYPU70LeooyDcwFX6YaOHxrjCNd8cmIjavnJCZ12eVkHI55eY4wlIhhUcf+KYzD+gkN9k0KEJmmN5JLbTcrKVyauCqvVHavcppRDZ3BInuyRhL3aAaDfSBJ1tnJBZAD2VsrgsUs35OqFevPNJdJwO90+1vfJEq1bYYb+0u8oF46ORqJVGYCScpeW+Rrs82dW20UFmJFDiQgw+EEVDakqAJlOZjZO18ZLxZXKW0skEJP1u/BeDb408c9PT6HNsRK72Grw1tjNHH+0JwR+ZgJQnGH+EHW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 09:33:27.9207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a92a227-0513-4220-c3a6-08df1d438d47 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF000264B0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7115 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260928_103340_936365_9C3FF239 X-CRM114-Status: GOOD ( 16.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Xilinx Versal NET, the ARM SMMUv3 EVENTQ, PRIQ and GERROR interrupts are routed through a vendor-specific Control and Status Register (CSR) block, where they must be enabled, cleared and acknowledged before being forwarded to the parent GIC. This series adds a small irqchip driver for the CSR block that chains to the standard arm-smmu-v3 driver, so the generic SMMUv3 driver needs no changes. Patch 1 adds the DT binding. Patch 2 adds the irqchip driver. Changes in v4: - irqchip driver (Sashiko): use handle_fasteoi_irq() + .irq_eoi() with IRQCHIP_EOI_THREADED so the sticky W1C status is cleared only after the threaded SMMUv3 handler drains the source, avoiding spurious interrupts. - dt-bindings: No changes, Added Acked-by:Conor Dooley tag Link to v3: https://lore.kernel.org/all/20260923-smmu-changes-v2-v3-0-87bd09ba9605@amd.com/ Changes in v3: - irqchip driver (Sashiko): harden against interrupt sources left enabled/latched by a prior boot stage: - Mask and clear every CSR source at init, including CMD_SYNC (bit 1) which the driver does not service. - Gate the handler on the mask register (ISR & ~MASK) instead of the raw ISR, so masked-but-latched sources are not dispatched. - Mask and clear any active source with no mapped consumer so it cannot spin the parent line. - dt-bindings: No changes Link to v2: https://lore.kernel.org/all/20260918-smmu-changes-v2-v2-0-adda681ab983@amd.com/#t Changes in v2: - Posted as a proper threaded series with a cover letter (v1 patches went out individually). - dt-bindings (Krzysztof): - Dropped the irrelevant arm,smmu-v3 consumer node from the example. - Dropped the unused "smmu_irq_csr" label from the example. - Dropped the redundant "binding" from the patch subject. - irqchip driver (Thomas): - Aligned kernel-doc member descriptions and used "interrupt" instead of "IRQ". - Used guard(raw_spinlock)() in the mask/unmask/ack callbacks and addressed the comments related to lock handling. - Thomas suggested using devm-managed allocation and irqdomain APIs; however, the driver is registered via IRQCHIP_DECLARE() and has no associated struct device, so devm APIs cannot be used. This code is left unchanged. Link to v1: https://lore.kernel.org/all/20260817105233.1557748-1-tushar.nimkar@amd.com/ https://lore.kernel.org/all/20260817105251.1557770-1-tushar.nimkar@amd.com/ Signed-off-by: Tushar Nimkar --- Anirudha Sarangi (2): dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR irqchip: Add Xilinx Versal NET SMMU CSR interrupt controller driver .../xlnx,versal-net-smmu-csr.yaml | 75 +++++++ MAINTAINERS | 10 + drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-xilinx-smmu-csr.c | 249 +++++++++++++++++++++ 5 files changed, 345 insertions(+) --- base-commit: 0d9d0dbf2fddcff5859d623e90ca73c4054276e1 change-id: 20260917-smmu-changes-v2-9cf7435d6969 Best regards, -- Tushar Nimkar