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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc78796cf39sm5448596a12.32.2026.09.28.19.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 19:09:00 -0700 (PDT) From: Joey Lu To: Vinod Koul , Neil Armstrong Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Catalin Marinas , Jacky Huang , Shan-Chun Hung , Hui-Ping Chen , Joey Lu , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v6 0/3] phy: nuvoton: extend MA35D1 USB2 PHY driver for dual-port OTG support Date: Tue, 29 Sep 2026 10:08:51 +0800 Message-ID: <20260929020854.1282339-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260928_190902_296194_DF51BA2D X-CRM114-Status: GOOD ( 17.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MA35D1 SoC has two USB PHY ports managed by a shared hardware block: - PHY0 (USB0): OTG port shared between the DWC2 gadget controller and the EHCI0/OHCI0 host controllers. A hardware mux automatically routes USB0 signals to the correct controller based on the USB ID pin state. - PHY1 (USB1): dedicated host-only port for EHCI1/OHCI1. This series extends the existing phy-ma35d1-usb2.c driver and its binding to cover both ports and add OTG role-switch support, while keeping full backward compatibility with existing device trees. Changes since v5: - dts: rename the hsusb pinctrl group node to hsusb-grp. - phy: keep the clock-stability polling when SUSPEND is already set, per review comment: > + if (val & USBPMISCR_PHY_SUSPEND(n)) > + return 0; Please keep the clock-stability polling when SUSPEND is already set. If the initial polling times out, SUSPEND remains set. A subsequent phy_init() call will then return success here without checking whether the PHY clocks have become stable. Skipping the reset sequence for an already-enabled PHY makes sense, but both paths should still check the ready bits. - phy: clear MISCFCR0_UHOVRCURH when nuvoton,oc-active-high is absent, per review comment: > + if (of_property_read_bool(pdev->dev.of_node, > + "nuvoton,oc-active-high")) The binding defines active-low as the default when this property is absent. Please also clear MISCFCR0_UHOVRCURH in that case, so the configured polarity does not depend on the state left by the bootloader. These are pre-merge fixups to patches 2 and 3, which are net-new code in this series, so the commit messages are otherwise unchanged. Joey Lu (3): dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port and OTG arm64: dts: nuvoton: ma35d1: add USB controllers and dual-port PHY node phy: nuvoton: phy-ma35d1-usb2: extend to dual-port with OTG support .../bindings/phy/nuvoton,ma35d1-usb2-phy.yaml | 44 ++- .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 36 +++ .../boot/dts/nuvoton/ma35d1-som-256m.dts | 36 +++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 65 ++++ drivers/phy/nuvoton/phy-ma35d1-usb2.c | 286 +++++++++++++----- 5 files changed, 390 insertions(+), 77 deletions(-) base-commit: cee9395acd8043be0644b25c34bfa86623f2b935 -- 2.43.0