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Mon, 28 Sep 2026 20:45:16 -0700 (PDT) Date: Tue, 29 Sep 2026 03:44:55 +0000 In-Reply-To: <20260929034510.2023173-1-praan@google.com> Mime-Version: 1.0 References: <20260929034510.2023173-1-praan@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260929034510.2023173-2-praan@google.com> Subject: [PATCH v11 01/16] iommu/arm-smmu-v3: Refactor arm_smmu_setup_irqs From: Pranjal Shrivastava To: iommu@lists.linux.dev Cc: Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Nicolin Chen , Daniel Mentz , Ashish Mhetre , linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Radu Rendec , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , rafael@kernel.org, Danilo Krummrich , driver-core@lists.linux.dev, Pranjal Shrivastava , Jason Gunthorpe Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260928_204518_421393_EF335DD6 X-CRM114-Status: GOOD ( 22.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Refactor arm_smmu_setup_irqs by splitting it into two parts, one for registering interrupt handlers and the other one for enabling interrupt generation in the hardware. This refactor helps in re-initialization of hardware interrupts as part of a subsequent patch that enables runtime power management for the arm-smmu-v3 driver. Additionally, pass a 'resume' flag to arm_smmu_device_reset() to skip registering IRQ handlers again during resume. On probe, handlers are registered after queues are configured but before enabling translation. Reviewed-by: Mostafa Saleh Reviewed-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Signed-off-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 75 +++++++++++++++------ 1 file changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 5732f3ba0122..270e6617a19a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4756,14 +4756,55 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) } } +static void arm_smmu_enable_irqs(struct arm_smmu_device *smmu) +{ + int ret; + u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; + + if (smmu->features & ARM_SMMU_FEAT_PRI) + irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; + + /* + * Enable interrupt generation on the SMMU. + * As per the ARM SMMUv3 spec section 6.3.17 (SMMU_IRQ_CTRL): + * + * Completion of an Update of x_IRQEN from 0 to 1 guarantees that the + * MSI configuration in SMMU_x_IRQ_CFG{0,1,2} will be used for all + * future MSIs generated from source x. All wired or MSI interrupts + * that are triggered from a source relate to occurrences that happened + * after the completion of the Update that enabled the source. It is + * not permitted to trigger an interrupt that relates to an occurrence + * that happened before the source was enabled, even if the source was + * previously enabled at the time of the occurrence. + */ + ret = arm_smmu_write_reg_sync(smmu, irqen_flags, + ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); + if (ret) + dev_warn(smmu->dev, "failed to enable irqs\n"); +} + +static int arm_smmu_disable_irqs(struct arm_smmu_device *smmu) +{ + return arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, + ARM_SMMU_IRQ_CTRLACK); +} + static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) { int ret, irq; - u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; - /* Disable IRQs first */ - ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, - ARM_SMMU_IRQ_CTRLACK); + /* + * Disable IRQs first as required by the Arm SMMUv3 spec. + * As per the ARM SMMUv3 spec section 6.3.17 (SMMU_IRQ_CTRL): + * + * An Update of x_IRQEN from 1 to 0 completes when all prior MSIs have + * completed. An MSI has completed when it is visible to its + * Shareability domain, or when it has aborted, and the abort is + * recorded in the appropriate SMMU_(*_)GERROR bit. Completion of this + * Update guarantees that no new MSI writes or wired edge events from + * source x become visible until the source is re-enabled. + */ + ret = arm_smmu_disable_irqs(smmu); if (ret) { dev_err(smmu->dev, "failed to disable irqs\n"); return ret; @@ -4785,15 +4826,6 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) } else arm_smmu_setup_unique_irqs(smmu); - if (smmu->features & ARM_SMMU_FEAT_PRI) - irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; - - /* Enable interrupt generation on the SMMU */ - ret = arm_smmu_write_reg_sync(smmu, irqen_flags, - ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); - if (ret) - dev_warn(smmu->dev, "failed to enable irqs\n"); - return 0; } @@ -4841,7 +4873,7 @@ static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG); } -static int arm_smmu_device_reset(struct arm_smmu_device *smmu) +static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume) { int ret; u32 reg, enables; @@ -4943,12 +4975,17 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) } } - ret = arm_smmu_setup_irqs(smmu); - if (ret) { - dev_err(smmu->dev, "failed to setup irqs\n"); - return ret; + if (!resume) { + ret = arm_smmu_setup_irqs(smmu); + if (ret) { + dev_err(smmu->dev, "failed to setup irqs\n"); + return ret; + } } + /* Enable interrupt generation on the SMMU */ + arm_smmu_enable_irqs(smmu); + if (is_kdump_kernel()) enables &= ~(CR0_EVTQEN | CR0_PRIQEN); @@ -5594,7 +5631,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev) arm_smmu_rmr_install_bypass_ste(smmu); /* Reset the device */ - ret = arm_smmu_device_reset(smmu); + ret = arm_smmu_device_reset(smmu, false); if (ret) { arm_smmu_device_disable(smmu); return ret; -- 2.56.0.rc1.315.gc6ed9934b7-goog