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Tue, 29 Sep 2026 00:19:55 -0700 (PDT) Date: Tue, 29 Sep 2026 07:19:42 +0000 In-Reply-To: <20260929071950.2710070-1-praan@google.com> Mime-Version: 1.0 References: <20260929071950.2710070-1-praan@google.com> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20260929071950.2710070-2-praan@google.com> Subject: [RFC PATCH v1 1/9] iommu/kho: Extend IOMMU KHO ABI for ARM SMMUv3 From: Pranjal Shrivastava To: iommu@lists.linux.dev, Will Deacon , Jason Gunthorpe Cc: Robin Murphy , Joerg Roedel , Nicolin Chen , Kevin Tian , Samiullah Khawaja , David Matlack , Vipin Sharma , Mostafa Saleh , Daniel Mentz , Pasha Tatashin , Pratyush Yadav , linux-arm-kernel@lists.infradead.org, kexec@lists.infradead.org, linux-kernel@vger.kernel.org, Pranjal Shrivastava Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260929_001957_117691_85823E45 X-CRM114-Status: GOOD ( 13.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Extend the KHO IOMMU ABI to support state preservation for Arm SMMUv3. Introduce struct iommu_smmuv3_hw_ser to capture SMMU hardware state, including the register base, Stream Table config and Live Update state tokens for the preserved Stream Tables. Additionally, introduce struct iommu_master_smmuv3_ser to capture per master state. For now it is used to preserve CD tables for Stage-1 translation. Signed-off-by: Pranjal Shrivastava --- include/linux/kho/abi/iommu.h | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/include/linux/kho/abi/iommu.h b/include/linux/kho/abi/iommu.h index 308cd83fd3e3..397fdb0449a6 100644 --- a/include/linux/kho/abi/iommu.h +++ b/include/linux/kho/abi/iommu.h @@ -82,6 +82,7 @@ enum iommu_type_ser { IOMMU_INVALID, IOMMU_INTEL, + IOMMU_ARM_SMMUV3, }; #define IOMMU_SER_FLAG_DELETED (1 << 0) @@ -142,6 +143,23 @@ struct iommu_device_intel_ser { u64 max_pasid; } __packed; +/** + * struct iommu_master_smmuv3_ser - SMMUv3 specific device state + * @l1_cdtab_lu_state: Live update state token for the linear/L1 CD table + * @num_l2_cdtables: Number of active L2 CD tables preserved + * @l2_cdtab_lu_states_phys: Physical pointer to an array of u64 LU state tokens + * for the active L2 CD tables (0 if linear) + * + * Note: Currently unused for Stage-2 Live Update. Reserved for future + * preservation of Stage-1 per-device Context Descriptor (CD) tables. + */ +struct iommu_master_smmuv3_ser { + u64 l1_cdtab_lu_state; + u32 num_l2_cdtables; + u32 padding; + u64 l2_cdtab_lu_states_phys; +} __packed; + /** * struct iommu_device_ser - Serialized state of a device * @hdr: Common object header @@ -159,6 +177,7 @@ struct iommu_device_ser { struct iommu_dev_map_ser domain_iommu_ser; union { struct iommu_device_intel_ser intel; + struct iommu_master_smmuv3_ser smmuv3; }; } __packed; @@ -181,6 +200,22 @@ struct iommu_intel_ser { u64 context_tables_bitmap[VTD_PRESERVED_BITMAP_LONGS]; }; +/** + * struct iommu_smmuv3_hw_ser - SMMUv3 specific hardware state + * @phys_addr: Physical address of the SMMU register base + * @strtab_base_cfg: STRTAB_BASE_CFG register value + * @l1_strtab_lu_state: Live update state token for the linear table OR the L1 table + * @l2_strtab_lu_states_phys: Physical pointer to an array of u64 LU state tokens + * indexed by L1 index, 0 for L2 tables that aren't + * preserved (0 if linear) + */ +struct iommu_smmuv3_hw_ser { + u64 phys_addr; + u64 strtab_base_cfg; + u64 l1_strtab_lu_state; + u64 l2_strtab_lu_states_phys; +} __packed; + /** * struct iommu_hw_ser - Serialized state of an IOMMU instance * @hdr: Common object header @@ -194,6 +229,7 @@ struct iommu_hw_ser { u64 type; union { struct iommu_intel_ser intel; + struct iommu_smmuv3_hw_ser smmuv3; }; } __packed; -- 2.56.0.rc1.315.gc6ed9934b7-goog