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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1790702811; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Subject:Subject:Date:Date:Message-Id:Message-Id:MIME-Version:Content-Type:Content-Transfer-Encoding:To:To:Cc:Cc:Reply-To; bh=uKbN1/2S72+Ds1i9QYOJgPbItX37Pf7LrEr2RrJNMN4=; b=q9JliJP0jLlP954Aqp+Kr1YUHjUf0M7ZEwkXLgClIxWO7tgXZzu6LHb3BQ6q5kvt qpk/BcEHv14/tz/PfYwNz6alvs3mrovAK2EgnsqTOkRAduAuPw+4kpVrWpl0/LM+Odo bJlkPug2cseu+GgF8sEfAFGplXcltN6E6Acv/toc= Received: by smtp.zohomail.com with SMTPS id 1790702810475424.1998192636315; Tue, 29 Sep 2026 10:26:50 -0700 (PDT) From: Junhui Liu Subject: [PATCH v5 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Date: Wed, 30 Sep 2026 01:26:07 +0800 Message-Id: <20260930-a733-clk-v5-0-11175b41cd2d@pigmoral.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/22QS2rDMBRFt2I0roJ+tiwTSvdROpCfnxLR+FPJM Skhe69sF+yWTARX6Jwr7p1EDB4jqbI7CTj56PsuhfwlI3C23Qmpb1ImgomCpYNaLSWFyydljXL AmDXOAEnPh4DO3xbV+0fKZx/HPnwv5onPt6tEcrZJJk4ZlUWt0NRCqVy/Df7U9sFeDiPCmcyiS Wyw5nwHiwQbrRpellAjg2ew3GDD8h0sE5wzJ2TppAFdPoPVDhb7ZjU3Ay8V1mgs8P/wYx0k4Nc 1TTquq5AWY7TLpFV2/P1SQeO1u/lF2/V0WCeBukHBwTgszF/367x1bSNS6NvWj1U26YOkAXhqf fwAgGvNKNABAAA= X-Change-ID: 20260202-a733-clk-0d4fc00a9f9c To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara , Krzysztof Kozlowski X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6367; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=p/GHIp4Q+wktNYmNZSYzDRjvrWbldK01OubfVytpjns=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLJ2f9m0uvIjT8M6D1kb3+js7l0rYgUSORcuef0+8kR5f T2/RoR3RykLgxgXg6yYIguXv/g/ax2eb0cEWu/DzGFlAhnCwMUpABPRkGX473w0OP7o+4LDr1zP hhaJWernXflodeDhu1O+3LF8J0tMXBj+cNybKnfYJUUmy7xlX4zCL7Ml3oWmB7T85jkKL5kifyC HFwA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260929_102721_573336_B83B0E3F X-CRM114-Status: GOOD ( 15.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the main CCU and the PRCM module (R-CCU) found in the Allwinner A733 SoC. The clock architecture is derived from the previous A523 design, with the MCU_CCU removed and the clock tree extended for the additional functional blocks found on the A733. The A733 introduces a "pll-ref" clock that normalizes the physical oscillator frequency, which can be 19.2MHz, 24MHz, or 26MHz, into a consistent 24MHz reference for the PLL clock tree. The peripheral, video, and DE PLLs provide multiple independently gated outputs with programmable dividers. Model these outputs as separate divider-and-gate child clocks. Also follow the documented hierarchy for the derived peripheral PLL outputs. The explicitly named PLL_AUDIO1 /2 and /5 outputs are modeled as fixed-factor clocks, with their divider fields initialized accordingly. Also extend the sunxi-ng SDM (Sigma-Delta Modulation) support for the dual-pattern register layout used by the A733 PLLs. PLL_AUDIO0 uses the dual-pattern SDM support to synthesize its fractional output. PLL_AUDIO1 does not expose fractional rates, but its SDM controls are modeled so that stale settings left by firmware can be disabled when an integer rate is programmed. The actual parents of a small number of bus gates are not documented in the user manual. Follow the vendor BSP and keep these gates parented to "hosc" until more complete hardware information is available. This series depends on the A523 single-divider clock fixes [1], which add feature support to the M-only clock macro used by the MBUS and DRAM0 clocks. The prerequisite series has been applied to the sunxi/clk-for-7.4 branch. Link: https://patch.msgid.link/20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech [1] Signed-off-by: Junhui Liu --- Changes in v5: - Add the CLK_GIC binding ID, inserted after CLK_TRACE - Add the GIC clock and mark it critical - Fix the continuation line alignment of the trace clock - Mark ahb-cpus critical - Link to v4: https://patch.msgid.link/20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech Changes in v4: - Model the MBUS and DRAM0 clocks as M-only clocks - Base the series on the A523 single-divider clock fixes - Link to v3: https://patch.msgid.link/20260905-a733-clk-v3-0-50f238f39c78@pigmoral.tech Changes in v3: - Patch 1: Rename the clock/reset binding headers with the allwinner vendor prefix, use BSD-2-Clause for their dual license, and reorder the binding properties according to the preferred schema layout - Patches 1 and 4: Drop the undocumented 12X suffix from the video and DE PLL core clock names and binding IDs - Patch 2: Require all PAT1 enable bits to be set when checking whether SDM is enabled - Patch 4: Model the independently gated peripheral, video, and DE PLL outputs as programmable-divider child clocks - Patch 4: Follow the documented hierarchy for the derived peripheral PLL outputs - Patch 4: Model the explicitly named PLL_AUDIO1 /2 and /5 outputs as fixed-factor clocks and initialize their divider fields accordingly - Patch 4: Model the PLL_AUDIO1 SDM controls so stale firmware settings are disabled when an integer rate is programmed - Patch 4: Add the missing module device table and remove an unused include - Patch 6: Replace the MP helpers used by timer clocks, which have no M divider, with the corresponding P-only helpers - Patch 7: Document the unresolved parents of bus gates kept on hosc and fix the APB/AHB IOMMU1 system clock names - Patches 3 and 8: Make the reset maps const - Link to v2: https://patch.msgid.link/20260711-a733-clk-v2-0-974d188cbe0c@pigmoral.tech Changes in v2: - Rework the clocks property in DT bindings to source hosc directly from the oscillator to adapt to the new RTC binding - Clean up the SDM dual-pattern helper macro and add the missing enable parameter for pll-audio0 - Number single-instance clocks with 0, e.g. GPU0, VE_ENC0/VE_DEC0, DRAM0, NAND0, GPADC0, THS0, etc - Correct 8x PLL post-divider names to 12x for video and DE PLLs (pll-videoX-12x, pll-de-12x) - Drop gic, cpu-peri, nsi clocks - Rename clocks: OWA -> SPDIF, USB_REF -> USB01_REF, HDMI_ESM -> HDCP_ESM, PWMCTRL -> PWM - Mark bus-dram0, ahb-store and mbus-store critical to avoid DMA, MMC and SPI NOR failures when unused clocks are disabled - Switch PRCM timer clocks to P-only helpers - Fix bus gate bit positions for UARTs and correct the sysdap register address - Interleave bus clocks into function clocks - Link to v1: https://lore.kernel.org/r/20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech --- Junhui Liu (8): dt-bindings: clk: sun60i-a733-ccu: Add Allwinner A733 support clk: sunxi-ng: sdm: Add dual patterns support clk: sunxi-ng: a733: Add PRCM CCU clk: sunxi-ng: a733: Add PLL clocks support clk: sunxi-ng: a733: Add bus clocks support clk: sunxi-ng: a733: Add mod clocks support clk: sunxi-ng: a733: Add bus clock gates clk: sunxi-ng: a733: Add reset lines .../bindings/clock/allwinner,sun60i-a733-ccu.yaml | 107 + drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile | 4 + drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 273 +++ drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 2406 ++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_sdm.c | 52 +- drivers/clk/sunxi-ng/ccu_sdm.h | 29 +- .../dt-bindings/clock/allwinner,sun60i-a733-ccu.h | 291 +++ .../clock/allwinner,sun60i-a733-r-ccu.h | 39 + .../dt-bindings/reset/allwinner,sun60i-a733-ccu.h | 129 ++ .../reset/allwinner,sun60i-a733-r-ccu.h | 23 + 11 files changed, 3337 insertions(+), 26 deletions(-) --- base-commit: e5e04726cdd043e309677071ab1b65a4b18f422b change-id: 20260202-a733-clk-0d4fc00a9f9c prerequisite-message-id: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> prerequisite-patch-id: 0df2ae41836b86fd868dfa01ddfde57f888f761a prerequisite-patch-id: 88f3a431e7c551a9fa732f062188f10fdd362eeb prerequisite-patch-id: 3e88bc873c909059d1199f82cda4013765e7a5e5 prerequisite-patch-id: 0dbc27cd7417352319a0705a051dff35085e8922 Best regards, -- Junhui Liu