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Wed, 30 Sep 2026 01:13:55 -0500 From: Colin Huang Date: Wed, 30 Sep 2026 14:10:15 +0800 Subject: [PATCH v9 07/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260930-anacapa-devlop-phase-devicetree-v9-7-f08aa0d7182d@gmail.com> References: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> In-Reply-To: <20260930-anacapa-devlop-phase-devicetree-v9-0-f08aa0d7182d@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Ryan Chen , Billy Tsai CC: , , , , , Colin Huang , Andy Chung X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790748641; l=3254; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=xSybis4WnZ0wCCi5yNlS7U3ZxSjvjItq7krEUM0miaU=; b=iqYCebzbVOrsbMqhLQIXSXleFW0jMCj9ofppclxzNnC7wvw2uJcT8G7SjDgCVIzRmjc/yx4pY 1HqEoB2S4d7CU0iHP3hSxeU24uF6jF5BlgvvRdhGEkh+3d8EcjbVFD5 X-Developer-Key: i=u8813345@gmail.com; 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Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 3ea5d67865d4..ab16e5ad5871 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,25 @@ #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" +&{/aliases} { + i2c36 = &i2c11mux0ch5; + i2c37 = &i2c11mux0ch6; + i2c38 = &i2c11mux0ch7; + i2c39 = &i2c11mux0ch0; + i2c40 = &i2c11mux0ch1; + i2c41 = &i2c11mux0ch2; + i2c42 = &i2c11mux0ch3; + i2c43 = &i2c11mux0ch4; + i2c44 = &i2c10mux0ch1; + i2c45 = &i2c10mux0ch2; + i2c46 = &i2c10mux0ch3; + i2c47 = &i2c10mux0ch4; + i2c48 = &i2c10mux0ch5; + i2c49 = &i2c10mux0ch6; + i2c50 = &i2c10mux0ch7; + i2c51 = &i2c10mux0ch0; +}; + // MB - PDB &i2c8 { i2c-mux@72 { @@ -50,6 +69,124 @@ eeprom@51 { }; }; +// R Bridge Board +&i2c10 { + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c10mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c10mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c10mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c10mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; +}; + +// L Bridge Board +&i2c11 { + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + mctp-controller; + // FE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; +}; + // MB &i2c13 { i2c-mux@70 { -- 2.34.1