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Each child node can carry its own reg, interrupts, iommus, and power-domains properties, describing a real per-channel MMIO region. Enables per-channel IOMMU stream ID assignment via the standard iommus property on each child. The interrupts property is removed from the required list since channels with child nodes carry their own interrupts. Existing DTS without child nodes remains valid. Assisted-by: LLM Signed-off-by: Peng Fan --- .../devicetree/bindings/dma/fsl,edma.yaml | 70 +++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index f609038e35ae..19a103baccaf 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -104,11 +104,40 @@ properties: Bit semantics: 0 means channel available, 1 means channel unavailable default: 0 + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + description: Per-channel register region within the eDMA block. + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + required: + - reg + required: - "#dma-cells" - compatible - reg - - interrupts - dma-channels allOf: @@ -351,3 +380,42 @@ examples: <&pd IMX_SC_R_DMA_3_CH6>, <&pd IMX_SC_R_DMA_3_CH7>; }; + + - | + #include + + dma-controller@42000000 { + compatible = "fsl,imx95-edma5"; + reg = <0x42000000 0x210000>; + #dma-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-channels = <64>; + clocks = <&clk 0>; + clock-names = "dma"; + + dma-channel@42020000 { + reg = <0x42020000 0x8000>; + interrupts = ; + iommus = <&smmu 0x30>; + }; + + dma-channel@42028000 { + reg = <0x42028000 0x8000>; + interrupts = ; + iommus = <&smmu 0x30>; + }; + + dma-channel@42030000 { + reg = <0x42030000 0x8000>; + interrupts = ; + iommus = <&smmu 0x31>; + }; + + dma-channel@42038000 { + reg = <0x42038000 0x8000>; + interrupts = ; + iommus = <&smmu 0x31>; + }; + }; -- 2.51.0