From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13C0FCA5FCB for ; Thu, 1 Oct 2026 11:07:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Z30FlrqlbcA0bfl7CltL26LpmBEQ96tPR9jwxaJO/aE=; b=0TjoQvJlOPZ9lxpTYmbp9nqTPa e0o2LYodAyjOqANKzWs8zUVvAwP6tNqHRpXn4wRRpDlc9J/7Br4HuNTIX3eEaRxKNozHXz1cuL3rs R+63JKDAnnc172OktfrjjcNKDkQ8gmsExGO/op6GpceQJN9mT0m7tY2KTeBaaPGs7qmbgiEVD1CyT faFROqwqToPWNl+cdpXbUX07KxOOIlHXr54VavaeBNZI7qJ/VdSDJhpWm/Aa15XFSfzakFIpZktar rFLpbtMYRPjmWDy//+WnqqVMQiiq3iy0tr1oYe9NNAl1Nk22LLTuTYVrQxFCwVYNYOutj0cY3R9hR hp+OlhUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xCEdR-00000008b2T-2ZZw; Thu, 01 Oct 2026 11:07:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xCEdO-00000008b18-0fWQ for linux-arm-kernel@lists.infradead.org; Thu, 01 Oct 2026 11:07:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF42A497; Thu, 1 Oct 2026 04:07:22 -0700 (PDT) Received: from e142392.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C2D2C3F86F; Thu, 1 Oct 2026 04:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790852846; bh=4DAiayNigTX+g+3g54tMOjDfHo5LSjI4E5QwkB1TMt8=; h=From:To:Cc:Subject:Date:From; b=SEqbRqgr7Bz+660L1PCMbE8pEbH+yVGsLlw5/TUkc5VwETrtJn6CmW4YF7beKF14p c5OJ8EJID75s14rq1YkXHLWwROvttTARh7Wx3BMQ8iUhi3T0p3mrJP+2kAdoAw4ilH PIzHvnnvNV9qlJG5latOLHXa/5+9amrEMabHoYbQ= From: =?UTF-8?q?Kristina=20Mart=C5=A1enko?= To: linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, kvmarm@lists.linux.dev, linux-efi@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Ryan Roberts , David Hildenbrand , Lorenzo Stoakes , Linu Cherian , Anshuman Khandual , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Ard Biesheuvel , Ilias Apalodimas Subject: [RFC 00/12] arm64: Add support for TLBI domains Date: Thu, 1 Oct 2026 12:06:43 +0100 Message-ID: <20261001110655.461473-1-kristina.martsenko@arm.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_040730_277993_85A82587 X-CRM114-Status: GOOD ( 21.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, This series allows the kernel to use TLBI domains. TLBI domains (FEAT_TLBID) is an Arm architecture feature that enables a TLB invalidation to target a subset of CPUs instead of the whole system. It can improve performance on systems with many CPUs. TLBID is not yet part of the Arm Architecture Reference Manual but some of it is described in the latest XML [1]. The goal of this series is to send TLBI commands only to the CPUs where a process has run (i.e. where its page tables have been installed). The last patch explains a bit about how it works. This is an RFC since I'm not familiar with the kernel's TLB/mm code and I'd like feedback on whether the general approach is correct. A few notes and open questions: * Domains are described in a new "TLBI" ACPI table. This is not yet part of the ACPI specification. There was an initial proposal [2] but this series uses a newer WIP version of the table that aims to be published by the end of the year. * There is currently no device tree binding since the feature is mainly meant for server-class systems. * It's also possible to use TLBI domains to limit a KVM guest's TLB invalidations to CPUs where the guest has run. I'll try to include that in the next version. This series only disables domains for guests. * With this series a long-running process may eventually run on all CPUs and just issue broadcast TLBIs. It may be worth periodically reducing the set of CPUs but it's not clear when. * There are currently no performance numbers since there is no hardware with this feature yet. * The series has been tested on an Arm FVP which supports the TLBID architecture but does not have any domains (except domain 0). Any feedback is welcome. Thanks, Kristina [1] https://support.arm.com/architectures/a-profile-architecture#Downloads [2] https://github.com/tianocore/edk2/issues/11999 Kristina Martšenko (12): arm64: sysreg: Add definitions for FEAT_TLBID arm64: Detect FEAT_TLBID KVM: arm64: Hide TLBID from guest sysregs KVM: arm64: Hide TLBID from guest instructions ACPICA: Add TLBI table definition ACPI: TLBI: Parse domains from table arm64: tlbid: Set up CPU domain bitmaps efi/arm: Check return value of init_new_context() arm64: tlbid: Track the TLBI domain of a task arm64: Support TLBIP instructions arm64: tlbid: Pass domain to TLBI instructions arm64: tlbid: Add documentation Documentation/arch/arm64/booting.rst | 10 ++ arch/arm64/Kconfig | 12 ++ arch/arm64/include/asm/acpi.h | 10 ++ arch/arm64/include/asm/cpu.h | 1 + arch/arm64/include/asm/cpufeature.h | 15 ++ arch/arm64/include/asm/el2_setup.h | 76 +++++++- arch/arm64/include/asm/kvm_emulate.h | 5 + arch/arm64/include/asm/mmu.h | 13 ++ arch/arm64/include/asm/mmu_context.h | 9 +- arch/arm64/include/asm/tlbflush.h | 219 +++++++++++++++++------- arch/arm64/kernel/cpufeature.c | 25 +++ arch/arm64/kernel/cpuinfo.c | 3 + arch/arm64/kvm/config.c | 6 + arch/arm64/kvm/emulate-nested.c | 1 + arch/arm64/kvm/hyp/include/hyp/switch.h | 7 +- arch/arm64/kvm/hyp/nvhe/tlb.c | 2 +- arch/arm64/kvm/hyp/vhe/tlb.c | 4 +- arch/arm64/kvm/sys_regs.c | 3 + arch/arm64/mm/Makefile | 1 + arch/arm64/mm/context.c | 6 +- arch/arm64/mm/tlbid.c | 210 +++++++++++++++++++++++ arch/arm64/tools/cpucaps | 1 + arch/arm64/tools/sysreg | 53 +++++- drivers/acpi/arm64/Kconfig | 3 + drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/init.c | 2 + drivers/acpi/arm64/init.h | 1 + drivers/acpi/arm64/tlbi.c | 196 +++++++++++++++++++++ drivers/firmware/efi/arm-runtime.c | 3 +- include/acpi/actbl2.h | 32 ++++ 30 files changed, 858 insertions(+), 72 deletions(-) create mode 100644 arch/arm64/mm/tlbid.c create mode 100644 drivers/acpi/arm64/tlbi.c base-commit: 93f51579e7df248780214094418f205253383cc5 -- 2.43.0