From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2E29CA5FB3 for ; Thu, 1 Oct 2026 11:07:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6/jpqy8qk8O3ebkjLGXZ/a155HCT4OEg23WO6w6wSCs=; b=oXXzvN7o2fK9OHoZ16uRgbe3WT HfpvcuGQZD7qdb1wFFO8mlwh/0HWi0mDfAI1ozlRlmVZCr3f+rBzNtXTZeidsJJYEEXx6MmTFpC8l 9wIqIROU6YHwxR4vCPA8b1OzKwuBR0+TIqXkikBhgnjmxxuFYYUNhyRZHFNV3z7KGLK3KAwo8uVJD sCTwGMpYF73Nkrk6GG7LK56Vtz29S2ut/0M3cB3K33XRXNwY9YcZ4AeKw96O6O3hZTLlDryKjkwVk po6xdjApnNgKLBiUeTz8cbkL8AF/quc7jfKd6oRBX/xojG56B9/8gwhI612N7cIaizrmPejX5mlfm jUuvrSgw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xCEdg-00000008bBp-0lh6; Thu, 01 Oct 2026 11:07:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1xCEdd-00000008b9Z-1c17 for linux-arm-kernel@lists.infradead.org; Thu, 01 Oct 2026 11:07:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BBD6497; Thu, 1 Oct 2026 04:07:41 -0700 (PDT) Received: from e142392.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 22E6C3F86F; Thu, 1 Oct 2026 04:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790852864; bh=sR/CLGnNZ6vKv3becO7CSItL3bbwT5ucdC5dew0i4z4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OYnirVMASiKdIlPSWq/DswGsA6PgeU3X5zIgbULY0rzM903MEcHUZya+xmJQu8NwJ 08ZRvyImxAC0kNKSAJGWUmR8xpjwZsIg+ln+QdV+jdCmRc/39rlSfDvJWmmmHp7Z5k b14DybkM8d/8abIZ84L9FL+xEJuk4H8iuCyoF53g= From: =?UTF-8?q?Kristina=20Mart=C5=A1enko?= To: linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, kvmarm@lists.linux.dev, linux-efi@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Ryan Roberts , David Hildenbrand , Lorenzo Stoakes , Linu Cherian , Anshuman Khandual , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Ard Biesheuvel , Ilias Apalodimas Subject: [RFC 04/12] KVM: arm64: Hide TLBID from guest instructions Date: Thu, 1 Oct 2026 12:06:47 +0100 Message-ID: <20261001110655.461473-5-kristina.martsenko@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261001110655.461473-1-kristina.martsenko@arm.com> References: <20261001110655.461473-1-kristina.martsenko@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_040745_519060_B0B6D92E X-CRM114-Status: GOOD ( 15.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since we don't expose TLBID to guests, try to hide TLBI domains from guest TLBI{P} instructions: * Map all guest virtual domains to the broadcast domain 0 in VTLBID{OS}_EL2. Enable the mapping with HCRX_EL2.VTLBID{OS}En. If the guest issues a TLBI to a TLBI domain, it will instead go to all agents in the Inner or Outer Shareable domain (as it does today). * TLBID introduces some TLBIP instructions. A guest can execute TLBIP instructions unless KVM or a nested hypervisor configures TLBI instructions to trap. If trapped, then a TLBIP will trap with EC 0x14. In this case KVM currently injects an UNDEF (and prints an error). This patch doesn't change that, as we don't support TLBIP instructions in guests. * KVM emulates some guest TLBI instructions. Ignore the TLBI domain in ASID* TLBI instructions. In other types of TLBIs the domain is implicitly ignored. (*ALL* instructions have the domain in an optional register argument, which KVM does not pass. *VA*/*IPA* instructions don't have a domain, only their TLBIP variants do.) Assisted-by: LLM Signed-off-by: Kristina Martšenko --- arch/arm64/include/asm/el2_setup.h | 67 +++++++++++++++++++++++++ arch/arm64/include/asm/kvm_emulate.h | 5 ++ arch/arm64/include/asm/tlbflush.h | 2 + arch/arm64/kvm/hyp/include/hyp/switch.h | 7 ++- arch/arm64/kvm/hyp/vhe/tlb.c | 2 + 5 files changed, 81 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index bd70a470596c..df8751fdc66d 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -189,6 +189,72 @@ msr vttbr_el2, xzr .endm +#define VTLBID_ISH 0 +#define VTLBID_OSH 1 + +.macro __init_vtlbid_regs sh + mrs_s x0, SYS_TLBIDIDR_EL1 + + .if \sh == VTLBID_ISH + ubfx x1, x0, #TLBIDIDR_EL1_NIS_SHIFT, #TLBIDIDR_EL1_NIS_WIDTH + ubfx x2, x0, #TLBIDIDR_EL1_NVIS_SHIFT, #TLBIDIDR_EL1_NVIS_WIDTH + .else + ubfx x1, x0, #TLBIDIDR_EL1_NOS_SHIFT, #TLBIDIDR_EL1_NOS_WIDTH + ubfx x2, x0, #TLBIDIDR_EL1_NVOS_SHIFT, #TLBIDIDR_EL1_NVOS_WIDTH + .endif + cbz x1, .Lskip_vtlbid_regs_\@ + + /* Map all virtual domains to the broadcast-all domain */ + .if \sh == VTLBID_ISH + msr_s SYS_VTLBID0_EL2, xzr + .else + msr_s SYS_VTLBIDOS0_EL2, xzr + .endif + + /* + * VTLBID1_EL2 is implemented if either NIS <= 8 && NVIS >= 4, + * or NIS > 8 && NVIS >= 3. Similarly for VTLBIDOS1_EL2. + */ + cmp x1, #8 + cset x0, ls + add x0, x0, #3 + cmp x2, x0 + b.lo .Lskip_vtlbid_regs_\@ + .if \sh == VTLBID_ISH + msr_s SYS_VTLBID1_EL2, xzr + .else + msr_s SYS_VTLBIDOS1_EL2, xzr + .endif + + /* + * VTLBID{2,3}_EL2 are implemented if either NIS <= 8 && NVIS >= 5, + * or NIS > 8 && NVIS >= 4. Similarly for VTLBIDOS{2,3}_EL2. + */ + add x0, x0, #1 + cmp x2, x0 + b.lo .Lskip_vtlbid_regs_\@ + .if \sh == VTLBID_ISH + msr_s SYS_VTLBID2_EL2, xzr + msr_s SYS_VTLBID3_EL2, xzr + .else + msr_s SYS_VTLBIDOS2_EL2, xzr + msr_s SYS_VTLBIDOS3_EL2, xzr + .endif +.Lskip_vtlbid_regs_\@: +.endm + +/* TLBID domain mapping */ +.macro __init_el2_vtlbid + mrs_s x0, SYS_ID_AA64MMFR4_EL1 + ubfx x0, x0, #ID_AA64MMFR4_EL1_TLBID_SHIFT, #ID_AA64MMFR4_EL1_TLBID_WIDTH + cbz x0, .Lskip_vtlbid_\@ + + __init_vtlbid_regs VTLBID_ISH + __init_vtlbid_regs VTLBID_OSH + +.Lskip_vtlbid_\@: +.endm + /* GICv3 system register access */ .macro __init_el2_gicv3 mrs x0, id_aa64pfr0_el1 @@ -469,6 +535,7 @@ __init_el2_brbe __init_el2_lor __init_el2_stage2 + __init_el2_vtlbid __init_el2_gicv3 __init_el2_gicv5 __init_el2_hstr diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index a3c1928bdf74..306e51fce221 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -734,6 +734,11 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) vcpu->arch.hcrx_el2 |= HCRX_EL2_NVnTTLBOS; } } + + if (cpus_have_final_cap(ARM64_HAS_TLBID)) + vcpu->arch.hcrx_el2 |= (HCRX_EL2_VTLBIDEn | + HCRX_EL2_VTLBIDOSEn); + } } diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 14a78ac0f800..b51df8e0ce63 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -46,6 +46,8 @@ __tlbi(op, (arg) | USER_ASID_FLAG); \ } while (0) +#define TLBI_TLBID_MASK GENMASK_ULL(15, 0) + /* This macro creates a properly formatted VA operand for the TLBI */ #define __TLBI_VADDR(addr, asid) \ ({ \ diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 1ce7130e2549..f67a4131c083 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -340,9 +340,12 @@ static inline void __deactivate_traps_mpam(void) * the PTW is a thing. It really isn't. * * - EnIDCP128: We don't allow IMPDEF sysregs -- full stop. + * + * - VTLBID{OS}En: We decide which domain the guest's TLBIs are broadcast to. */ -#define NV_HCRX_GUEST_EXCLUDE (HCRX_EL2_TMEA | HCRX_EL2_PTTWI | \ - HCRX_EL2_EnIDCP128) +#define NV_HCRX_GUEST_EXCLUDE (HCRX_EL2_TMEA | HCRX_EL2_PTTWI | \ + HCRX_EL2_EnIDCP128 | HCRX_EL2_VTLBIDEn | \ + HCRX_EL2_VTLBIDOSEn) static inline void __activate_traps_common(struct kvm_vcpu *vcpu) { diff --git a/arch/arm64/kvm/hyp/vhe/tlb.c b/arch/arm64/kvm/hyp/vhe/tlb.c index c386d9f1c101..e2e6a2df1533 100644 --- a/arch/arm64/kvm/hyp/vhe/tlb.c +++ b/arch/arm64/kvm/hyp/vhe/tlb.c @@ -226,6 +226,7 @@ void __kvm_flush_vm_context(void) * - a non-shareable TLBI is upgraded to being inner-shareable * - an outer-shareable TLBI is also mapped to inner-shareable * - an nXS TLBI is upgraded to XS + * - any TLBID domain is upgraded to broadcast-all */ int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding) { @@ -291,6 +292,7 @@ int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding) case OP_TLBI_ASIDE1NXS: case OP_TLBI_ASIDE1ISNXS: case OP_TLBI_ASIDE1OSNXS: + va &= ~TLBI_TLBID_MASK; __tlbi(aside1is, va); break; case OP_TLBI_VAAE1: -- 2.43.0