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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4f46bb550sm5016692a91.5.2026.10.01.06.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 06:18:24 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v2 0/3] spi: Add Nuvoton MA35D1 SPI controller support Date: Thu, 1 Oct 2026 21:18:15 +0800 Message-Id: <20261001131818.110028-1-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_061827_346734_28454EFE X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Chi-Wen Weng This series adds support for the SPI controller found on the Nuvoton MA35D1 SoC. The MA35D1 provides separate SPI and QSPI controller IPs. They expose the same Devicetree-visible resources and provide up to two native chip selects, so the existing MA35D1 QSPI binding is extended to also cover the SPI controller. The SPI driver supports host mode using polling-based PIO transfers, SPI modes 0 through 3, 8 to 32 bits per word, LSB-first transfers, native chip selects and GPIO chip selects. The PIO path also honors per-word delays requested through struct spi_transfer. The existing MA35D1 QSPI driver is updated separately to support GPIO chip selects through the SPI core. SPI-mem operations for devices using GPIO chip selects fall back to the regular SPI transfer path, while native chip selects continue to use the controller's SSCTL register. This series is based on the current broonie/spi.git for-7.4 branch and therefore includes the already applied MA35D1 QSPI reset handling and DTR follow-up fixes. Changes in v2: - Extend the existing MA35D1 QSPI binding to also cover the SPI controller. - Add GPIO chip-select support to the MA35D1 QSPI driver and allow cs-gpios in the shared binding. - Remove the unnecessary SSCTL spinlock from the SPI driver. - Cache the controller clock rate instead of querying it for every transfer. - Rely on the SPI core for transfer defaults and validation. - Avoid disabling and re-enabling the controller when the transfer configuration has not changed. - Add per-word delay handling to the SPI PIO transfer path. - Add system sleep support using the SPI core suspend/resume helpers. - Rebase on the current broonie/spi.git for-7.4 branch. Based on: broonie/spi.git for-7.4 93914f171867 ("Add enhance SPI DMA support for JHB100 SFC") Chi-Wen Weng (3): spi: dt-bindings: nuvoton,ma35d1-qspi: Add MA35D1 SPI controller spi: ma35d1: Add Nuvoton MA35D1 SPI controller support spi: ma35d1-qspi: Add GPIO chip select support .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 41 +- drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + drivers/spi/spi-ma35d1-qspi.c | 39 +- drivers/spi/spi-ma35d1.c | 716 ++++++++++++++++++ 5 files changed, 799 insertions(+), 9 deletions(-) create mode 100644 drivers/spi/spi-ma35d1.c base-commit: 93914f1718676aec13ccd3787642c8b05e2b8309 -- 2.25.1