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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4f46bb550sm5016692a91.5.2026.10.01.06.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 06:18:38 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v2 3/3] spi: ma35d1-qspi: Add GPIO chip select support Date: Thu, 1 Oct 2026 21:18:18 +0800 Message-Id: <20261001131818.110028-4-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261001131818.110028-1-cwweng.linux@gmail.com> References: <20261001131818.110028-1-cwweng.linux@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_061842_738402_F1176ED9 X-CRM114-Status: GOOD ( 19.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Chi-Wen Weng The generic SPI controller binding allows GPIO-based chip selects, but the MA35D1 QSPI driver does not currently enable the SPI core's GPIO descriptor handling. Enable GPIO chip-select support and specify that the controller provides two native chip selects. Add a setup callback to reject active-high polarity only for native chip selects, while allowing GPIO chip selects to use the polarity handled by the GPIO subsystem. This keeps the binding capable of describing valid board wiring while preserving the active-low limitation of the controller's native chip selects. Signed-off-by: Chi-Wen Weng --- drivers/spi/spi-ma35d1-qspi.c | 39 ++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 30e3239f777d..0644bb2990b8 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -62,7 +62,7 @@ #define NUVOTON_QSPI_STATUS_RXEMPTY_MASK BIT(8) /* Receive FIFO Empty */ #define NUVOTON_QSPI_STATUS_BUSY_MASK BIT(0) /* Busy Status */ -#define NUVOTON_QSPI_MAX_NUM_CS 2 +#define NUVOTON_QSPI_MAX_NATIVE_CS 2 #define NUVOTON_QSPI_DEFAULT_NUM_CS 2 #define NUVOTON_QSPI_DEFAULT_BPW 8 /* Bound PIO operations to avoid long atomic polling loops. */ @@ -442,13 +442,35 @@ static void nuvoton_qspi_set_cs_level(struct nuvoton_qspi *qspi, spin_unlock_irqrestore(&qspi->ssctl_lock, flags); } +static int nuvoton_qspi_setup(struct spi_device *spi) +{ + unsigned int cs = spi_get_chipselect(spi, 0); + + if (spi_get_csgpiod(spi, 0)) + return 0; + + if (cs >= NUVOTON_QSPI_MAX_NATIVE_CS) { + dev_err(&spi->dev, "invalid native chip select %u\n", cs); + return -EINVAL; + } + + if (spi->mode & SPI_CS_HIGH) { + dev_err(&spi->dev, + "active-high native chip select is not supported\n"); + return -EINVAL; + } + + return 0; +} + static void nuvoton_qspi_set_cs(struct spi_device *spi, bool level) { struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); /* - * The SPI core passes the physical CS level to ->set_cs(). This - * initial driver only supports active-low native chip selects. + * GPIO chip selects are handled by the SPI core. For native chip + * selects, the core passes the physical CS level to ->set_cs(). + * Native chip selects are active low. */ nuvoton_qspi_set_cs_level(qspi, spi_get_chipselect(spi, 0), !level); } @@ -457,7 +479,11 @@ static void nuvoton_qspi_mem_set_cs(struct spi_device *spi, bool assert) { struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); - /* The direct spi-mem path passes a logical assertion state. */ + /* + * Direct spi-mem operations are only executed for native chip + * selects. GPIO chip selects use the regular SPI fallback path. + * This helper takes a logical assertion state. + */ nuvoton_qspi_set_cs_level(qspi, spi_get_chipselect(spi, 0), assert); } @@ -638,18 +664,21 @@ static int nuvoton_qspi_probe(struct platform_device *pdev) goto err_assert; } - if (!num_cs || num_cs > NUVOTON_QSPI_MAX_NUM_CS) { + if (!num_cs || num_cs > NUVOTON_QSPI_MAX_NATIVE_CS) { ret = dev_err_probe(dev, -EINVAL, "invalid num-cs %u\n", num_cs); goto err_assert; } ctlr->num_chipselect = num_cs; + ctlr->max_native_cs = NUVOTON_QSPI_MAX_NATIVE_CS; + ctlr->use_gpio_descriptors = true; ctlr->max_transfer_size = nuvoton_qspi_max_transfer_size; ctlr->max_message_size = nuvoton_qspi_max_message_size; ctlr->mem_ops = &nuvoton_qspi_mem_ops; ctlr->mem_caps = &nuvoton_qspi_mem_caps; ctlr->dtr_caps = true; + ctlr->setup = nuvoton_qspi_setup; ctlr->set_cs = nuvoton_qspi_set_cs; ctlr->transfer_one = nuvoton_qspi_transfer_one; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); -- 2.25.1