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Thu, 01 Oct 2026 14:33:58 -0700 (PDT) Date: Thu, 1 Oct 2026 21:33:56 +0000 In-Reply-To: <5750151d-cb99-4f9d-b469-12a7b7796985@linaro.org> Mime-Version: 1.0 References: <20260924172928.2110956-1-coltonlewis@google.com> <5750151d-cb99-4f9d-b469-12a7b7796985@linaro.org> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20261001213357.2088894-2-coltonlewis@google.com> Subject: Re: [PATCH v9 00/22] ARM64 PMU Partitioning From: Colton Lewis To: James Clark Cc: Colton Lewis , Marc Zyngier , Oliver Upton , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Fuad Tabba , Catalin Marinas , Will Deacon , Mark Rutland , Paolo Bonzini , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Robin Murphy , Zide Chen , Alexandru Elisei , Ganapatrao Kulkarni , Mingwei Zhang , Jonathan Corbet , Russell King , Shuah Khan , linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_143400_627576_C37935E9 X-CRM114-Status: GOOD ( 21.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, On Wed, Sep 30, 2026 at 04:26:23PM +0100, James Clark wrote: > On 24/09/2026 18:29, Colton Lewis wrote: > > This series creates a new PMU scheme on ARM, a partitioned PMU that > > allows reserving a subset of counters for more direct guest access, > > significantly reducing overhead. More details, including performance > > benchmarks, can be read in the v1 cover letter linked below. > > > > There is no longer a kernel command line parameter > > (`arm_pmuv3.reserved_host_counters`); PMU partitioning is now completely > > controlled via the KVM API using `KVM_ARM_VCPU_PMU_V3_ENABLE_PARTITION` > > and `KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS` vCPU device attributes. When > > As far as I know there isn't a straightforward way to get the number of hw > counters from userspace. You have to either parse dmesg or attempt to open > incrementally more counters in a group until it fails. > > This makes doing things like "use all counters for guest" or "reserve two > for the host" difficult. Maybe it's time to add a file to the PMU that > userspace can use query this. Inside a VMM, userspace can query the default PMCR_EL0.N via KVM_GET_ONE_REG(SYS_PMCR_EL0) after KVM_ARM_VCPU_INIT (or KVM_ARM_VCPU_PMU_V3_SET_PMU) and before calling KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS, since KVM initializes nr_pmu_counters to the PMU's max_counters (which is how vpmu_counter_access discovers the limit). For users and management tools outside the VMM (e.g. choosing N to pass on the QEMU command line), I agree it's awkward that /sys/bus/event_source/devices//caps/ exposes slots and bus_width but not the number of counters. I will add a patch to expose a caps attribute for the number of counters in drivers/perf/arm_pmuv3.c. Thanks, Colton