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[207.179.239.100]) by smtp-relay.gmail.com with ESMTPS id af79cd13be357-93cca1ea26fsm54885385a.3.2026.10.01.19.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 19:57:51 -0700 (PDT) X-Relaying-Domain: ausil.us From: Dennis Gilmore To: linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Alexey Charkov , Heiko Stuebner , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Dennis Gilmore Subject: [PATCH] arm64: dts: rockchip: Use GPIO function for PCIe reset on Orange Pi 5 Pro Date: Thu, 1 Oct 2026 21:57:46 -0500 Message-ID: <20261002025746.3284691-1-dennis@ausil.us> X-Mailer: git-send-email 2.55.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_195754_014437_26A0275E X-CRM114-Status: GOOD ( 15.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PERST# pins of pcie2x1l1 and pcie2x1l2 are used as reset-gpios, but the default pinctrl state muxes them to the controllers' dedicated PERST# function instead of GPIO. Linux happens to work because the pin is switched to GPIO function when it is requested as a GPIO, but the devicetree should describe the pin function the board actually uses. Bootloaders such as U-Boot apply the pinctrl state as described and do not change the function when the GPIO is requested, and probing pcie2x1l2 then hangs. Add GPIO pinctrl nodes for both reset pins and use them in place of the PERST# function, like other RK3588 boards do. Fixes: f47af8ebbe53 ("arm64: dts: rockchip: Add Orange Pi 5 Pro board support") Signed-off-by: Dennis Gilmore --- .../boot/dts/rockchip/rk3588s-orangepi-5-pro.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts index c9679bac1db7..783675337ab9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts @@ -188,7 +188,7 @@ package_fan1: package-fan1 { /* NVMe */ &pcie2x1l1 { pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1m1_1_perstn>, <&pcie30x1m1_1_clkreqn>, + pinctrl-0 = <&pcie2_1_rst>, <&pcie30x1m1_1_clkreqn>, <&pcie30x1m1_1_waken>; reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; supports-clkreq; @@ -199,7 +199,7 @@ &pcie2x1l1 { /* NIC */ &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie20x1m0_perstn>, <&pcie20x1m0_clkreqn>, + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>; reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_eth>; @@ -223,6 +223,16 @@ ethernet_en: ethernet-en { }; }; + pcie { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_otg_en: vcc5v0-otg-en { rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; -- 2.55.0