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Fri, 02 Oct 2026 02:10:08 -0700 (PDT) Received: from mi-OptiPlex-7060.mioffice.cn ([43.224.245.234]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e49f6ab2b9sm5480555ad.36.2026.10.02.02.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2026 02:10:06 -0700 (PDT) From: Wen Jiang X-Google-Original-From: Wen Jiang To: akpm@linux-foundation.org, catalin.marinas@arm.com, linux-mm@kvack.org, urezki@gmail.com, will@kernel.org Cc: Xueyuan.chen21@gmail.com, ajd@linux.ibm.com, anshuman.khandual@arm.com, baohua@kernel.org, chleroy@kernel.org, david@kernel.org, dev.jain@arm.com, jiangwen6@xiaomi.com, leo.yan@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, rppt@kernel.org, ryan.roberts@arm.com Subject: [PATCH v10 02/10] powerpc/8xx: add pte_set_huge() Date: Fri, 2 Oct 2026 17:09:39 +0800 Message-Id: <20261002090947.869220-3-jiangwen6@xiaomi.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261002090947.869220-1-jiangwen6@xiaomi.com> References: <20261002090947.869220-1-jiangwen6@xiaomi.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261002_021009_575497_17A32C73 X-CRM114-Status: GOOD ( 15.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org vmap installs PTE-level block mappings (SZ_16K/SZ_512K on powerpc/8xx) by reusing set_huge_pte_at(), a HugeTLB helper gated by CONFIG_HUGETLB_PAGE. This makes the feature silently unavailable on CONFIG_HUGETLB_PAGE=n kernels and couples mm/vmalloc.c to HugeTLB internals it does not otherwise need. Add pte_set_huge() to powerpc/8xx, next to the existing pmd_clear_huge()/pud_clear_huge() in mm/nohash/8xx.c. It builds the huge PTE and writes it into the backing cells directly, without going through set_huge_pte_at(), so it does not depend on CONFIG_HUGETLB_PAGE. No pte_clear_huge() is needed: 8xx does not implement arch_vmap_pte_range_unmap_size(), so the vmap unmap path never takes the PTE-clearing branch. In practice PPC_8xx selects HUGETLBFS unconditionally, so CONFIG_HUGETLB_PAGE=n does not occur there today; this is a decoupling cleanup rather than a new configuration. There is no caller yet: mm/vmalloc.c is converted later in this series, once the generic fallbacks are in place. Signed-off-by: Wen Jiang Reviewed-by: Christophe Leroy (CS GROUP) --- arch/powerpc/include/asm/nohash/32/pte-8xx.h | 4 +++ arch/powerpc/mm/nohash/8xx.c | 29 ++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h index e2ea8ba9f8cae..1ee3f8f0de974 100644 --- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h @@ -235,6 +235,10 @@ static inline pte_t ptep_get(pte_t *ptep) } #endif /* CONFIG_PPC_16K_PAGES */ +#define __HAVE_ARCH_PTE_SET_HUGE +void pte_set_huge(pte_t *ptep, unsigned long addr, phys_addr_t phys, + pgprot_t prot, unsigned long size); + #endif #endif /* __KERNEL__ */ diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c index a9d3f4729eada..2518d2a6bdb41 100644 --- a/arch/powerpc/mm/nohash/8xx.c +++ b/arch/powerpc/mm/nohash/8xx.c @@ -220,3 +220,32 @@ int pmd_clear_huge(pmd_t *pmd) { return 0; } + +/* + * vmap PTE-level block mapping. Sets a present kernel mapping directly, + * so unlike set_huge_pte_at() it needs neither CONFIG_HUGETLB_PAGE nor + * set_pte_filter() (a no-op for non-exec kernel mappings). + */ +void pte_set_huge(pte_t *ptep, unsigned long addr, phys_addr_t phys, + pgprot_t prot, unsigned long size) +{ + pmd_t *pmdp = pmd_off(&init_mm, addr); + pte_t pte = pfn_pte(PHYS_PFN(phys), prot); + pte_basic_t val; + pte_basic_t *entry = (pte_basic_t *)ptep; + int num, i; + + pte = arch_make_huge_pte(pte, ilog2(size), 0); + val = pte_val(pte); + + /* + * Make sure hardware valid bit is not set. We don't do + * tlb flush for this update. + */ + VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep)); + + num = number_of_cells_per_pte(pmdp, val, 1); + + for (i = 0; i < num; i++, entry++, val += SZ_4K) + *entry = val; +} -- 2.34.1